Check for '#ifdef MIPS1', not '#ifndef MIPS3', since we can now have both.
Add runtime check for 'if (CPUISMIPS3)' inside #ifdef MIPS3. Add runtime check for 'if (!CPUISMIPS3)' inside #ifdef MIPS1.
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2c7d61677f
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.20 1997/06/16 23:41:53 jonathan Exp $ */
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/* $NetBSD: pmap.c,v 1.21 1997/06/17 01:38:21 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -251,8 +251,9 @@ pmap_bootstrap(firstaddr)
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* when Entry LO and Entry HI G bits are anded together
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* they will produce a global bit to store in the tlb.
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*/
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for(i = 0, spte = Sysmap; i < Sysmapsize; i++, spte++)
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spte->pt_entry = MIPS3_PG_G;
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if (CPUISMIPS3)
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for(i = 0, spte = Sysmap; i < Sysmapsize; i++, spte++)
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spte->pt_entry = MIPS3_PG_G;
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#endif
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}
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@ -458,9 +459,11 @@ pmap_release(pmap)
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pte = pmap->pm_segtab->seg_tab[i];
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if (!pte)
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continue;
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#ifndef MIPS3
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vm_page_free1(
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PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
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#ifdef MIPS1
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if (!(CPUISMIPS3)) {
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vm_page_free1(
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PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
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}
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#endif
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#ifdef DIAGNOSTIC
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for (j = 0; j < NPTEPG; j++) {
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@ -468,11 +471,16 @@ pmap_release(pmap)
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panic("pmap_release: segmap not empty");
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}
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#endif
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#ifdef MIPS3
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MachHitFlushDCache((vm_offset_t)pte, PAGE_SIZE);
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vm_page_free1(
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PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
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#endif
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if (CPUISMIPS3) {
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MachHitFlushDCache((caddr_t)pte, PAGE_SIZE);
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vm_page_free1(
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PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
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}
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#endif /* mips3 */
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pmap->pm_segtab->seg_tab[i] = NULL;
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}
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s = splimp();
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@ -541,10 +549,11 @@ pmap_remove(pmap, sva, eva)
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if (mips_pg_wired(entry))
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pmap->pm_stats.wired_count--;
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pmap->pm_stats.resident_count--;
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if(pmap_remove_pv(pmap, sva, pfn_to_vad(entry))) {
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if (pmap_remove_pv(pmap, sva, pfn_to_vad(entry))) {
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#ifdef MIPS3
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MachFlushDCache(sva, PAGE_SIZE);
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#endif
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if (CPUISMIPS3)
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MachFlushDCache(sva, PAGE_SIZE);
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#endif /* mips3 */
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}
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#ifdef ATTR
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pmap_attributes[atop(pfn_to_vad(entry))] = 0;
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@ -598,8 +607,9 @@ pmap_remove(pmap, sva, eva)
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pmap->pm_stats.resident_count--;
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if(pmap_remove_pv(pmap, sva, pfn_to_vad(entry))) {
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#ifdef MIPS3
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MachFlushDCache(sva, PAGE_SIZE);
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#endif
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if (CPUISMIPS3)
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MachFlushDCache(sva, PAGE_SIZE);
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#endif /* mips3 */
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}
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#ifdef ATTR
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pmap_attributes[atop(pfn_to_vad(entry))] = 0;
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@ -967,8 +977,8 @@ pmap_enter(pmap, va, pa, prot, wired)
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* between R/W and R/O pages.
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* NOTE: we only support cache flush for read only text.
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*/
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#ifndef MIPS3
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if (prot == (VM_PROT_READ | VM_PROT_EXECUTE)) {
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#ifdef MIPS1
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if ((!CPUISMIPS3) && prot == (VM_PROT_READ | VM_PROT_EXECUTE)) {
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MachFlushICache(MACH_PHYS_TO_CACHED(pa), PAGE_SIZE);
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}
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#endif
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@ -1062,7 +1072,7 @@ pmap_enter(pmap, va, pa, prot, wired)
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pte++;
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} while (--i != 0);
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#ifdef MIPS3
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if (prot == (VM_PROT_READ | VM_PROT_EXECUTE)) {
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if (CPUISMIPS3 && (prot == (VM_PROT_READ | VM_PROT_EXECUTE))) {
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#ifdef DEBUG
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if (pmapdebug & PDB_ENTER)
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printf("pmap_enter: flush I cache va %lx (%lx)\n",
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@ -1250,9 +1260,11 @@ pmap_zero_page(phys)
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printf("pmap_zero_page(%lx)\n", phys);
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#endif
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#ifdef MIPS3
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(phys, NBPG);
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if (CPUISMIPS3) {
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(phys, NBPG);
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}
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#endif
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p = (int *)MACH_PHYS_TO_CACHED(phys);
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end = p + PAGE_SIZE / sizeof(int);
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@ -1265,9 +1277,11 @@ pmap_zero_page(phys)
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p += 4;
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} while (p != end);
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#ifdef MIPS3
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(phys, NBPG);
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if (CPUISMIPS3) {
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(phys, NBPG);
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}
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#endif
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}
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@ -1287,9 +1301,11 @@ pmap_copy_page(src, dst)
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printf("pmap_copy_page(%lx, %lx)\n", src, dst);
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#endif
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#ifdef MIPS3
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache(); */
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MachFlushDCache(src, NBPG);
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if (CPUISMIPS3) {
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache(); */
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MachFlushDCache(src, NBPG);
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}
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#endif
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s = (int *)MACH_PHYS_TO_CACHED(src);
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d = (int *)MACH_PHYS_TO_CACHED(dst);
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@ -1307,9 +1323,11 @@ pmap_copy_page(src, dst)
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d += 4;
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} while (s != end);
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#ifdef MIPS3
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(dst, NBPG);
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if (CPUISMIPS3) {
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/*XXX FIXME Not very sophisticated */
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/* MachFlushCache();*/
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MachFlushDCache(dst, NBPG);
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}
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#endif
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}
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