for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write. (Writing can, of
course, be quite dangerous.)
with a MIPS4 option at this point -- all the code except for one single
spot is conditionalized with MIPS3. So, don't even pretend about
MIPS4 for now, until it all gets cleaned up.
for mips3 (and later) 'ld' and 'sd' instructions. These currently
only are properly implemented for the _MIPS_BSD_API_LP32 and
_MIPS_BSD_API_LP32_64CLEAN 'API's. They're pretty messy, but when you
need them, you really need them.
you do not save it and pass it along in rval the system will start
to fail running user programs. This finishes the suggestion by cgd to
not save some registers on syscall entry.
that the page being zero'd was not completed and that page zeroing
should be aborted. This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.
in syscall() anymore. By defition, processor was in SR_INT_IE turn
on prior to have syscall exception. MIPS1 assembler hook arranges
to enable the bit for its own. MIPS3 does the same effect by
turning off EXL bit.
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
to call syscall() kernel entry point. IEp is always 1 in this case
by defition.
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364
uses 2^(9+IC) and 2^(9+DC).
abstract around the problem by making the base a parameter to the
MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init
to mips3_vector_init and to mips3_ConfigCache (where it is used).
XXX: someone with an MIPS3_4100 should switch to this and get rid
of the ugly ifdefs in cpuregs.h
a whole 0.01us in lmbench lat_syscall null on our 250Mhz QED system.
$at is still saved just to be safe, although it looks like it does
not need to be. $v1 is used in syscall(), although I'm not sure why.
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.
it look at casual inspection like 1 nop is needed but play other tricks.
Still have reduced by 1 nop. Hopefully this covers the NEC 41[x]1. Could
not find info for those processors.
in the non-MULTIPROCESSOR case (LOCKDEBUG requires it). Scheduler
lock is held upon entry to mi_switch() and cpu_switch(), and
cpu_switch() releases the lock before returning.
Largely from Bill Sommerfeld, with some minor bug fixes and
machine-dependent code hacking from me.
- MB_LEN_MAX is increased to 32.
- To ensure binary compatibility for old executables
under multibyte locale, versioned setlocale is added.
- __mb_len_cur definision is added in setlocale.c
and enable it in stdlib.h .
It is also important for multibyte locale stuffs,
but I just forgot.
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss. Since this is now done in both
ICache flush routines, no need to do it in pmap.c. Fixed R4400
stability problems with setregs() cache flushing.
is illegal to flush on user addresses. In theory the race exists
on MIPS1, but it is rather unlikely in common use. I have
seen it with regress/sys/kern/sigtramp on a QED 5231 system.
Previously we jal to panic which never cleared the tlb fault, so if
on the course of shutdown (like a doshutdownhooks() callback) missed
K2, it would panic again. Fix by setting EPC to panic() and eret.
By default this is off, and only slightly changes the code to load SR when
a temp register is available. This can be used by the platform code to
handle slow to clear interrupts (our case) or to mask off any interrupt
any interrupt at run-time. This can be very useful for embedded platforms
that have less than desirable interrupt properties.
it would hang-up. logstacktrace() actually was the same as stacktrace() so
just make it an XLEAF() for now. Include some DDB code for KGDB compilation.
on mips3 systems, until the kernel actually hooks the vectors.
This makes it easier to debug early problems if the firmware
has provides an exception handler.
This keeps the SR management more contained in locore, and should
be roughly the same performance as the .text size is less. Talked
to simonb and he was ok with this change.
jhawk. This callback is used by platform code to manage things like
watchdogs that should be disabled while in ddb. Done as a callback
for processors such as mips that support lots of different systems.
Add ddb support for QED opcodes, fill in enough routines so "next" usually
works, kdbpoke support for any size. Add callback that ports can hook when
entering and leaving ddb. This can be used for things like turning
off watchdogs while in ddb.
This lets mips ports have additional machdep sysctl. Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4. Add cpu_intr()
prototype so this is defined in one place.
* put #includes of opt headers and headers to get protos used by
net/netisr_dispatch.h in net/netisr.h (if !defined(_LOCORE)) (rather than
in netisr_dispatch.h itself, and potentially nowhere, respectively).
* require netisr.h to be included before netisr_dispatch.h.
* minor additional cleanup of both netisr.h and netisr_dispatch.h.
* clean up uses to remove now-unnecessary header file inclusions, and
local prototypes of the fns.
* convert netisr dispatch implementations which didn't use
netisr_dispatch.h (pc532) to use it.
<vm/pglist.h> -> <uvm/uvm_pglist.h>
<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
<vm/vm_object.h> -> nothing
<vm/vm_pager.h> -> into <uvm/uvm_pager.h>
also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.
"off_t" and the return value is a "paddr_t" to allow mappings
at offsets past 2^31 bytes. Somewhat inspired by FreeBSD, which
only changed the offset to a "vm_offset_t".
Includes updates for the i386, pc532 and sh3 mmmmap from Jason Thorpe.
family) that usually occur in cold marine waters and often have barbels
and three dorsal fins.
code: a set of instructions for a computer.
The latter is more appropriate in the comment corrected here.
use them. Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think... Finally,
actually use them for every bloody cache op.
Merge Kernel MCOUNT and user MCOUNT.
The earlier code which was inserted to call _mcount in profiling
assembler routines is busted badly. This gets it working with PIC
code and should work with any arbitrary assembler routine.
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.
asm statements, obsoluting asm routines in locore.S. They are
designed to work in symmetry as names suggests. savefpregs()
does not clear a global variable fpcurproc. Both would be noops when
NOFPU global symbol is defined.
- MDP_FPUSED flag is not turned on for FPA-less processors like Vr4100
and TX3900 even when processes execute FP insns.
- Nuke external function reference of savefpregs() which is already defined
in mips/cpu.h.
- Adjust the comment tells "let user processes change CP0 status register
freely might be dangerous."
- MDP_FPUSED flag indicates the process has executed at least one
FP insn during its life time.
- pcb_fpregs storage is guaranteed zero initialzed. If the process is FPA
owner, savefpregs() must be called to synchronize it with FPA contents.
- No necessity to save FPA contents into pcb_fpregs prior to the whole
storage is overwritten by process_write_fpregs().
doing a cpu_set_kpc(), just pass the entry point and argument all
the way down the fork path starting with fork1(). In order to
avoid special-casing the normal fork in every cpu_fork(), MI code
passes down child_return() and the child process pointer explicitly.
This fixes a race condition on multiprocessor systems; a CPU could
grab the newly created processes (which has been placed on a run queue)
before cpu_set_kpc() would be performed.
- Change ktrace interface to pass in the current process, rather than
p->p_tracep, since the various ktr* function need curproc anyway.
- Add curproc as a parameter to mi_switch() since all callers had it
handy anyway.
- Add a second proc argument for inferior() since callers all had
curproc handy.
Also, miscellaneous cleanups in ktrace:
- ktrace now always uses file-based, rather than vnode-based I/O
(simplifies, increases type safety); eliminate KTRFLAG_FD & KTRFAC_FD.
Do non-blocking I/O, and yield a finite number of times when receiving
EWOULDBLOCK before giving up.
- move code duplicated between sys_fktrace and sys_ktrace into ktrace_common.
- simplify interface to ktrwrite()
state into global and per-CPU scheduler state:
- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues), sched_slpque (sleep queues).
NOTE: These may collectively move into a struct schedstate
at some point in the future.
- Per-CPU state, struct schedstate_percpu: spc_runtime
(time process on this CPU started running), spc_flags
(replaces struct proc's p_schedflags), and
spc_curpriority (usrpri of processes on this CPU).
- Every platform must now supply a struct cpu_info and
a curcpu() macro. Simplify existing cpu_info declarations
where appropriate.
- All references to per-CPU scheduler state now made through
curcpu(). NOTE: this will likely be adjusted in the future
after further changes to struct proc are made.
Tested on i386 and Alpha. Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.
from db_stack_trace_cmd() to db_stack_trace_print(),
and add an additional argument, a function pointer for an
output routine (i.e. printf() or db_printf()).
Add db_stack_trace_cmd() in db_command.[ch], calling
db_stack_trace_print() with db_printf() as the printer.
Move count==-1 special handling from db_stack_trace_print() [nee
db_stack_trace_cmd()] to db_stack_trace_cmd() [nascent here].
Again, I'm unable to test compilation on all affected platforms,
so advance apologies for potential brokenness.
which indicates that the process is actually running on a
processor. Test against SONPROC as appropriate rather than
combinations of SRUN and curproc. Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.
- Add 16 bytes to the stack on entry to _mcount so we don't
overflow it.
- Use inline interrupt {dis,en}abling instead of calling
profiled function in locore.
from Jeff Smith <jeffs@geocast.com>. These are needed to support
-mips2 compilation. With this change, on a QED 5231 we now pass the
paranoia tests, and are successfully using userlands built with -mips2.
use MIPS_TBRPL(). When PTEs are modified, both src and dst TLBs
are invalidated. MIPS3 single TLB entry has paired double PTE
and pagemove() likely walks through multiple pages. The positive
effect of of MachTLBUpdate() or TBRPL() is unclear.
implementation of locore routines between MIPS1 and MIPS3. It's
independent from mips_locore_jumpvec_t which is for cache/TLB
manipulating routines peculiar to processor designs. mips_locore_jumpvec_t
will be replaced with "processor closures" encapsulating implementation
parameters (cpuinfo) and pointers to conventaion routines (cpuops),
eventually.
discard MachTLBUpdate() calls, however, the necessity of TLB entry
modification in such a way is under question because implementation
glitches on ASID management was straightened, those calls can be
sanely removed after all.
contains the values __SIMPLELOCK_LOCKED and __SIMPLELOCK_UNLOCKED, which
replace the old SIMPLELOCK_LOCKED and SIMPLELOCK_UNLOCKED. These files
are also required to supply inline functions __cpu_simple_lock(),
__cpu_simple_lock_try(), and __cpu_simple_unlock() if locking is to be
supported on that platform (i.e. if MULTIPROCESSOR is defined in the
_KERNEL case). Change these functions to take an int * (&alp->lock_data)
rather than the struct simplelock * itself.
These changes make it possible for userland to use the locking primitives
by including <machine/lock.h>.
The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.
Fix regress/lib/libc/ieeefp/except for MIPS. Newer FPE handling code
did not generate SIGFPE, but always SIGILL. Add this back to the
assembly code. The QED 5231 requests the kernel emulates some of
the conditions that generate an SIGFPE, but when the emulation code
did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
Fix this by saving the fp regs earlier, then saving the new FSR in
the context. This allows the FSR value to be seen by the SIGFPE
handler.
Add fp emulation for 8 mips2 fpu instructions to handle exceptions
(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt). This lets
perl5 run when compiled -mips2.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that. Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.
This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.
Fix tested by Havard Eidnes.
half-baked and resulted in one superfluous ASID bump if new pmaps
are created when pmap_asid_generation > 0. Need to initialize pmap
fields correctly.
Yet, this possibly might not be the perfect solution. If one
process bumped pmap_asid_generation _after_ a new pmap was created
and initialized with then-current pmap_asid_generation value. In
that case, the new pmap would have another (superfluous) ASID bump
when 2nd (not 1st) CPU tick is assigned. I'm not sure if this case
would happen.
Have pmap_max_asid variable to hold the maximum number of ASID
(TLBpid) supported by processor anticipating the possible runtime
cost of ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS).
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.
- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
make them type-generic, which is necessary i.e. to operate on file offsets
without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
integral type (paddr_t, vaddr_t).
Originally done by Chuck Silvers, updated by myself.
(which disables the interrupts) is *not* a good idea. k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
don't stomp on the return address in k0. Also, don't need to account
for any load delays, as the last register restored (gp) isn't used in
the subsequent instruction.
nisimura