IDT32364's Config register uses a different base for IC/DC (instruction
and data cache sizes). R4000 uses 2^(12+IC) and 2^(12+DC). IDT32364 uses 2^(9+IC) and 2^(9+DC). abstract around the problem by making the base a parameter to the MIPS3_CONFIG_CACHE_SIZE macro. we pass the base down from mips_vector_init to mips3_vector_init and to mips3_ConfigCache (where it is used). XXX: someone with an MIPS3_4100 should switch to this and get rid of the ugly ifdefs in cpuregs.h
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chuck
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@ -1,4 +1,4 @@
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/* $NetBSD: cpuregs.h,v 1.35 2000/07/17 23:35:13 jeffs Exp $ */
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/* $NetBSD: cpuregs.h,v 1.36 2000/09/16 00:04:57 chuck Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -291,13 +291,15 @@
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#define MIPS3_CONFIG_DC_SHIFT 6
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#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
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#define MIPS3_CONFIG_IC_SHIFT 9
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#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
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#ifdef MIPS3_4100 /* VR4100 core */
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/* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */
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#define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \
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((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift)))
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#else
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
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(0x1000 << (((config) & (mask)) >> (shift)))
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
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((base) << (((config) & (mask)) >> (shift)))
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#endif
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/* Block ordering: 0: sequential, 1: sub-block */
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.41 2000/09/13 01:20:41 chuck Exp $ */
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/* $NetBSD: locore.h,v 1.42 2000/09/16 00:04:57 chuck Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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@ -62,7 +62,7 @@ void mips1_wbflush(void);
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void mips1_proc_trampoline(void);
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void mips1_cpu_switch_resume(void);
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void mips3_ConfigCache(void);
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void mips3_ConfigCache(int);
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void mips3_FlushCache(void);
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void mips3_FlushDCache(vaddr_t addr, vaddr_t len);
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void mips3_FlushICache(vaddr_t addr, vaddr_t len);
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@ -1,4 +1,4 @@
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/* $NetBSD: mips_machdep.c,v 1.100 2000/09/13 01:53:01 nisimura Exp $ */
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/* $NetBSD: mips_machdep.c,v 1.101 2000/09/16 00:04:57 chuck Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -52,7 +52,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.100 2000/09/13 01:53:01 nisimura Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.101 2000/09/16 00:04:57 chuck Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_compat_ultrix.h"
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@ -94,7 +94,7 @@ static void mips1_vector_init __P((void));
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#endif
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#ifdef MIPS3
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static void mips3_vector_init __P((void));
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static void mips3_vector_init __P((int));
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#endif
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mips_locore_jumpvec_t mips_locore_jumpvec;
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@ -210,18 +210,19 @@ mips_locore_jumpvec_t mips3_locore_vec =
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*----------------------------------------------------------------------------
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*/
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void
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mips3_ConfigCache()
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mips3_ConfigCache(mips3_csizebase)
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int mips3_csizebase;
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{
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u_int32_t config = mips3_read_config();
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static int snoop_check = 0;
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int i;
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mips_L1ICacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
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MIPS3_CONFIG_IC_MASK, MIPS3_CONFIG_IC_SHIFT);
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MIPS3_CONFIG_IC_MASK, mips3_csizebase, MIPS3_CONFIG_IC_SHIFT);
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mips_L1ICacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
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MIPS3_CONFIG_IB);
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mips_L1DCacheSize = MIPS3_CONFIG_CACHE_SIZE(config,
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MIPS3_CONFIG_DC_MASK, MIPS3_CONFIG_DC_SHIFT);
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MIPS3_CONFIG_DC_MASK, mips3_csizebase, MIPS3_CONFIG_DC_SHIFT);
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mips_L1DCacheLSize = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
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MIPS3_CONFIG_DB);
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@ -252,7 +253,8 @@ mips3_ConfigCache()
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}
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static void
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mips3_vector_init()
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mips3_vector_init(mips3_csizebase)
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int mips3_csizebase;
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{
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/* r4000 exception handler address and end */
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@ -289,7 +291,7 @@ mips3_vector_init()
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/*
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* Clear out the I and D caches.
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*/
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mips3_ConfigCache();
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mips3_ConfigCache(mips3_csizebase);
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#ifdef pmax /* XXX */
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mips_L2CachePresent = 1;
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@ -336,6 +338,9 @@ mips3_vector_init()
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void
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mips_vector_init()
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{
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#ifdef MIPS3
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int mips3_csizebase = MIPS3_CONFIG_C_DEFBASE;
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#endif
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/*
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* Copy exception-dispatch code down to exception vector.
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@ -417,6 +422,23 @@ mips_vector_init()
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mips_num_tlb_entries = 64;
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mips3_L1TwoWayCache = 1;
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break;
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#if 0 /* not ready yet */
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case MIPS_RC32364:
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/*
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* the IDT RC32364 core is a 32 bit MIPS2 processor with
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* MIPS3/MIPS4 extensions (e.g. it has an R4000-style TLB).
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* all registers are 32 bits (64 bit instructions like
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* ld/sd/dmfc0/dmtc0 are not allowed.
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*
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* note that the Config register has a non-standard base
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* for IC and DC (2^9 instead of 2^12).
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*/
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cpu_arch = 3;
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mips_num_tlb_entries = 16; /* each entry maps 2 pages */
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mips3_L1TwoWayCache = 1; /* note: line size is 16bytes */
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mips3_csizebase = 0x200; /* non-standard base in Config */
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break;
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#endif
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#endif /* MIPS3 */
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default:
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@ -443,7 +465,7 @@ mips_vector_init()
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mips3_locore_vec.flushDCache = mips3_FlushDCache_2way;
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mips3_locore_vec.flushICache = mips3_FlushICache_2way;
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}
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mips3_vector_init();
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mips3_vector_init(mips3_csizebase);
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memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));
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break;
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#endif
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