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Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like 

the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss.  Since this is now done in both
ICache flush routines, no need to do it in pmap.c.  Fixed R4400
stability problems with setregs() cache flushing.
This commit is contained in:
jeffs 2000-08-01 23:38:26 +00:00
parent 5e985516ea
commit e1cf55c8a8
2 changed files with 10 additions and 6 deletions
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9
sys/arch/mips/mips/locore_mips3.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips3.S,v 1.43 2000/07/25 18:06:49 jeffs Exp $ */
/* $NetBSD: locore_mips3.S,v 1.44 2000/08/01 23:38:26 jeffs Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -1564,7 +1564,7 @@ END(mips3_FlushCache)
* vaddr_t addr; vsize_t len;
*
* Flush instruction cache for range of addr to addr + len - 1.
* The address can be any valid address so long as no TLB misses occur.
* The address is reduced to a kseg0 index.
* Assumes a cache line size of 16 bytes for speed.
*
* Results:
@ -1577,7 +1577,12 @@ END(mips3_FlushCache)
*----------------------------------------------------------------------------
*/
LEAF(mips3_FlushICache)
lw a2, mips_L1ICacheSize
addu a2, -1
and a0, a0, a2 # get index into primary cache
addu a1, 127 # Align
li a2, MIPS_KSEG0_START
addu a0, a0, a2
srl a1, a1, 7 # Number of unrolled loops
1:
cache C_IINV_I, 0(a0)

7
sys/arch/mips/mips/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.104 2000/07/20 18:33:43 jeffs Exp $ */
/* $NetBSD: pmap.c,v 1.105 2000/08/01 23:38:26 jeffs Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -78,7 +78,7 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.104 2000/07/20 18:33:43 jeffs Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.105 2000/08/01 23:38:26 jeffs Exp $");
/*
* Manages physical address maps.
@ -969,8 +969,7 @@ pmap_procwr(p, va, len)
printf("pmap_procwr: va %lx len %lx\n", va, len);
#endif
MachFlushDCache(va, len);
MachFlushICache(MIPS_PHYS_TO_KSEG0(va &
(mips_L1ICacheSize - 1)), len);
MachFlushICache(va, len);
#endif /* MIPS3 */
} else {
#ifdef MIPS1