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use mips3 cache op. 

invalidate -> write-back invalidate
(although NetBSD/hpcmips run on write-through mode.)
suggested by cgd.
This commit is contained in:
uch 2000-07-10 16:23:18 +00:00
parent 5a5452c95d
commit e8ebb2a377
2 changed files with 32 additions and 30 deletions
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17
sys/arch/mips/include/r3900regs.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: r3900regs.h,v 1.2 2000/05/23 04:21:40 soren Exp $ */
/* $NetBSD: r3900regs.h,v 1.3 2000/07/10 16:23:18 uch Exp $ */
/*
* Copyright (c) 1999, by UCHIYAMA Yasushi
@ -123,18 +123,11 @@
#define R3900_CONFIG_DRSIZE_MASK 0x00000003
/*
* R3900 CACHE instruction (not MIPS3 cache op)
* R3900 CACHE
*/
#define R3900_MIN_CACHE_SIZE 1024
#define R3900_MAX_DCACHE_SIZE (8 * 1024)
#ifndef OP_CACHE
#define OP_CACHE 057
#endif
#define R3900_CACHE(op, offset, base) \
.word (OP_CACHE << 26 | ((base) << 21) | ((op) << 16) | \
((offset) & 0xffff))
#define R3900_CACHE_I_INDEXINVALIDATE 0
#define R3900_CACHE_D_HITINVALIDATE 0x11
#define CPUREG_A0 4
#define CPUREG_T0 8
#define R3900_CACHE_I_INDEX_INVALIDATE 0
#define R3900_CACHE_D_INDEX_WRITEBACK_INVALIDATE 0
#define R3900_CACHE_D_HITINVALIDATE 0x11

45
sys/arch/mips/mips/locore_mips1.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips1.S,v 1.35 2000/06/26 02:55:46 nisimura Exp $ */
/* $NetBSD: locore_mips1.S,v 1.36 2000/07/10 16:23:19 uch Exp $ */
/*
* Copyright (c) 1992, 1993
@ -1328,7 +1328,10 @@ LEAF(mips1_FlushDCache)
lw t0, mips_L1DCacheLSize
addu a1, a1, a0 # compute ending address
1:
R3900_CACHE(R3900_CACHE_D_HITINVALIDATE, 0, CPUREG_A0)
.set push
.set mips3
cache R3900_CACHE_D_INDEX_WRITEBACK_INVALIDATE, 0(a0)
.set pop
addu a0, a0, t0
bne a0, a1, 1b
nop
@ -1359,14 +1362,17 @@ LEAF(mips1_FlushICache)
addu a1, 127
srl a1, a1, 7 # Number of unrolled loops
3:
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, CPUREG_A0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, CPUREG_A0)
.set push
.set mips3
cache R3900_CACHE_I_INDEX_INVALIDATE, 0(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 16(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 32(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 48(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 64(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 80(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 96(a0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 112(a0)
.set pop
addu a1, -1
bne a1, zero, 3b
addu a0, 128
@ -1408,14 +1414,17 @@ LEAF(mips1_FlushCache)
addu t1, t0, t1 # End address
subu t1, t1, 128
3:
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 0, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 16, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 32, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 48, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 64, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 80, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 96, CPUREG_T0)
R3900_CACHE(R3900_CACHE_I_INDEXINVALIDATE, 112, CPUREG_T0)
.set push
.set mips3
cache R3900_CACHE_I_INDEX_INVALIDATE, 0(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 16(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 32(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 48(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 64(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 80(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 96(t0)
cache R3900_CACHE_I_INDEX_INVALIDATE, 112(t0)
.set pop
bne t0, t1, 3b
addu t0, t0, 128