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rename mips_read_causereg -> mips_cp0_cause_read. nuke prototype

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for mips_read_statusreg (which was apparently never implemented).
Provide prototypes and implementations for mips_cp0_cause_write,
mips_cp0_status_read, and mips_cp0_status_write.  (Writing can, of
course, be quite dangerous.)
This commit is contained in:
cgd 2000-10-04 22:44:01 +00:00
parent bb4b4d9e39
commit e9e1084ea3
3 changed files with 60 additions and 27 deletions
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8
sys/arch/mips/include/locore.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.45 2000/10/03 23:15:58 cgd Exp $ */
/* $NetBSD: locore.h,v 1.46 2000/10/04 22:44:01 cgd Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -45,8 +45,10 @@ struct tlb;
* only to print them by name in stack tracebacks
*/
u_int32_t mips_read_causereg(void);
u_int32_t mips_read_statusreg(void);
u_int32_t mips_cp0_cause_read(void);
void mips_cp0_cause_write(u_int32_t);
u_int32_t mips_cp0_status_read(void);
void mips_cp0_status_write(u_int32_t);
int mips1_icsize(void);
int mips1_dcsize(void);

66
sys/arch/mips/mips/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.115 2000/09/05 01:24:51 soren Exp $ */
/* $NetBSD: locore.S,v 1.116 2000/10/04 22:44:02 cgd Exp $ */
/*
* Copyright (c) 1992, 1993
@ -1067,28 +1067,60 @@ END(_remque)
#endif
/*----------------------------------------------------------------------------
/*
* u_int32_t mips_cp0_cause_read(void)
*
* mips_read_causereg --
* Return the current value of the CP0 Cause register.
*
* Return the current value of the cause register.
*
* int mips_read_causereg(void)
*
* Results:
* current value of Cause register.
*
* Side effects:
* None.
* Not profiled, skews CPU-clock measurement to uselessness.
*
*----------------------------------------------------------------------------
* Note: Not profiled, skews CPU-clock measurement (mips_mcclock.c)
* to uselessness.
*/
LEAF_NOPROFILE(mips_read_causereg)
LEAF_NOPROFILE(mips_cp0_cause_read)
mfc0 v0, MIPS_COP_0_CAUSE
j ra
nop
END(mips_read_causereg)
END(mips_cp0_cause_read)
/*
* void mips_cp0_cause_write(u_int32_t)
*
* Set the value of the CP0 Cause register.
*/
LEAF(mips_cp0_cause_write)
mtc0 a0, MIPS_COP_0_CAUSE
nop
nop
j ra
nop
END(mips_cp0_cause_write)
/*
* u_int32_t mips_cp0_status_read(void)
*
* Return the current value of the CP0 Status register.
*/
LEAF(mips_cp0_status_read)
mfc0 v0, MIPS_COP_0_STATUS
j ra
nop
END(mips_cp0_status_read)
/*
* void mips_cp0_status_write(u_int32_t)
*
* Set the value of the CP0 Status register.
*
* Note: This is almost certainly not the way you want to write a
* "permanent" value to to the CP0 Status register, since it gets
* saved in trap frames and restores.
*/
LEAF(mips_cp0_status_write)
mtc0 a0, MIPS_COP_0_STATUS
nop
nop
j ra
nop
END(mips_cp0_status_write)
#if !defined(NOFPU) || defined(SOFTFLOAT)
/*----------------------------------------------------------------------------

13
sys/arch/mips/mips/mips_mcclock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_mcclock.c,v 1.9 2000/03/28 02:58:49 simonb Exp $ */
/* $NetBSD: mips_mcclock.c,v 1.10 2000/10/04 22:44:02 cgd Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -34,7 +34,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_mcclock.c,v 1.9 2000/03/28 02:58:49 simonb Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_mcclock.c,v 1.10 2000/10/04 22:44:02 cgd Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -45,6 +45,7 @@ __KERNEL_RCSID(0, "$NetBSD: mips_mcclock.c,v 1.9 2000/03/28 02:58:49 simonb Exp
#include <dev/dec/mcclock_pad32.h>
#include <mips/cpu.h> /* CPUISMIPS3 */
#include <mips/locore.h> /* mips_cp0_cause_read() */
#include <mips/mips/mips_mcclock.h>
@ -52,8 +53,6 @@ unsigned mips_mc_cpuspeed __P((void *, int, int (*)(void *, int)));
int mips_mcclock_tickloop __P((void *, int));
unsigned mips_mcclock_to_mhz __P((unsigned iters));
u_int mips_read_causereg __P((void));
/*
* Compute MHz and DELAY() constants using the default
@ -157,7 +156,7 @@ mips_mcclock_tickloop(mcclock_addr, clockmask)
junk++; junk++; junk++; junk++;
/* Poll clock interrupt, waiting for next tick to happen. */
while ((mips_read_causereg() & clockmask) == 0)
while ((mips_cp0_cause_read() & clockmask) == 0)
;
/* Ack the mc146818 interrupt caused by starting tick. */
@ -167,12 +166,12 @@ mips_mcclock_tickloop(mcclock_addr, clockmask)
/* Count loops until next tick-interrupt request occurs (4ms). */
if (CPUISMIPS3) {
while ((mips_read_causereg() & clockmask) == 0) {
while ((mips_cp0_cause_read() & clockmask) == 0) {
__asm __volatile ("nop; nop; nop; nop");
iters++;
}
} else {
while ((mips_read_causereg() & clockmask) == 0) {
while ((mips_cp0_cause_read() & clockmask) == 0) {
__asm __volatile ("nop; nop;");
iters++;
}