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clean up and consistency for CP0 Count, Compare, Wired, and Config

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access function names and prototypes.
This commit is contained in:
cgd 2000-10-05 02:36:44 +00:00
parent 9366f12ec0
commit 59706f1322
11 changed files with 141 additions and 174 deletions
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4
sys/arch/arc/arc/arc_trap.c
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@ -1,4 +1,4 @@
/* $NetBSD: arc_trap.c,v 1.15 2000/08/02 08:57:15 soda Exp $ */
/* $NetBSD: arc_trap.c,v 1.16 2000/10/05 02:36:44 cgd Exp $ */
/* $OpenBSD: trap.c,v 1.22 1999/05/24 23:08:59 jason Exp $ */
/*
@ -165,7 +165,7 @@ cpu_intr(status, cause, pc, ipending)
* Writing a value to the Compare register,
* as a side effect, clears the timer interrupt request.
*/
mips3_write_compare(mips3_cycle_count());
mips3_cp0_compare_write(mips3_cp0_count_read());
}
#endif

4
sys/arch/arc/arc/wired_map.c
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@ -1,4 +1,4 @@
/* $NetBSD: wired_map.c,v 1.4 2000/06/29 08:34:10 mrg Exp $ */
/* $NetBSD: wired_map.c,v 1.5 2000/10/05 02:36:44 cgd Exp $ */
/*-
* Copyright (C) 2000 Shuichiro URATA. All rights reserved.
@ -85,7 +85,7 @@ arc_enter_wired(va, pa0, pa1, pg_size)
wired_map[nwired].size = MIPS3_PG_SIZE_MASK_TO_SIZE(pg_size);
/* Allocate new wired entry */
mips3_SetWIRED(MIPS3_TLB_WIRED_UPAGES + nwired + 1);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES + nwired + 1);
/* Map to it */
tlb.tlb_mask = pg_size;

6
sys/arch/cobalt/cobalt/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.22 2000/09/24 12:32:34 jdolecek Exp $ */
/* $NetBSD: machdep.c,v 1.23 2000/10/05 02:36:44 cgd Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@ -499,8 +499,8 @@ cpu_intr(status, cause, pc, ipending)
}
if (ipending & MIPS_INT_MASK_5) {
cycles = mips3_cycle_count();
mips3_write_compare(cycles + 1250000); /* XXX */
cycles = mips3_cp0_count_read();
mips3_cp0_compare_write(cycles + 1250000); /* XXX */
#if 0
cf.pc = pc;

6
sys/arch/hpcmips/hpcmips/machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.34 2000/09/24 12:32:34 jdolecek Exp $ */
/* $NetBSD: machdep.c,v 1.35 2000/10/05 02:36:45 cgd Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -43,7 +43,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.34 2000/09/24 12:32:34 jdolecek Exp $");
__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.35 2000/10/05 02:36:45 cgd Exp $");
/* from: Utah Hdr: machdep.c 1.63 91/04/24 */
#include "opt_vr41x1.h"
@ -729,7 +729,7 @@ cpu_intr(status, cause, pc, ipending)
* Writing a value to the Compare register,
* as a side effect, clears the timer interrupt request.
*/
mips3_write_compare(mips3_cycle_count());
mips3_cp0_compare_write(mips3_cp0_count_read());
}
#endif

20
sys/arch/mips/include/locore.h
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@ -1,4 +1,4 @@
/* $NetBSD: locore.h,v 1.48 2000/10/05 01:06:06 cgd Exp $ */
/* $NetBSD: locore.h,v 1.49 2000/10/05 02:36:45 cgd Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@ -78,7 +78,6 @@ void mips3_TBIAP(int);
void mips3_TBIS(vaddr_t);
int mips3_TLBUpdate(u_int, u_int);
void mips3_TLBRead(int, struct tlb *);
void mips3_SetWIRED(int);
void mips3_wbflush(void);
void mips3_proc_trampoline(void);
void mips3_cpu_switch_resume(void);
@ -88,12 +87,17 @@ void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len);
void mips3_HitFlushDCache_2way(vaddr_t, int);
void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len);
u_int32_t mips3_read_config(void);
u_int32_t mips3_cycle_count(void);
u_int32_t mips3_write_count(u_int32_t);
u_int32_t mips3_read_compare(void);
void mips3_write_config(u_int32_t);
void mips3_write_compare(u_int32_t);
u_int32_t mips3_cp0_compare_read(void);
void mips3_cp0_compare_write(u_int32_t);
u_int32_t mips3_cp0_config_read(void);
void mips3_cp0_count_write(u_int32_t);
u_int32_t mips3_cp0_count_read(void);
void mips3_cp0_config_write(u_int32_t);
u_int32_t mips3_cp0_wired_read(void);
void mips3_cp0_wired_write(u_int32_t);
u_int64_t mips3_ld(u_int64_t *);
void mips3_sd(u_int64_t *, u_int64_t);

4
sys/arch/mips/include/rnd.h
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@ -1,4 +1,4 @@
/* $NetBSD: rnd.h,v 1.2 2000/06/09 04:24:22 soda Exp $ */
/* $NetBSD: rnd.h,v 1.3 2000/10/05 02:36:45 cgd Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@ -51,7 +51,7 @@ cpu_hascounter(void)
static __inline u_int32_t
cpu_counter(void)
{
return mips3_cycle_count();
return mips3_cp0_count_read();
}
#endif

239
sys/arch/mips/mips/locore_mips3.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore_mips3.S,v 1.56 2000/10/05 01:06:06 cgd Exp $ */
/* $NetBSD: locore_mips3.S,v 1.57 2000/10/05 02:36:45 cgd Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -1244,53 +1244,6 @@ LEAF(mips3_SetPID)
nop
END(mips3_SetPID)
/*--------------------------------------------------------------------------
*
* mips3_SetWIRED --
*
* Write the given value into the TLB wired reg.
*
* mips3_SetWIRED(wired)
* int wired;
*
* Results:
* None.
*
* Side effects:
* WIRED set in the wired register.
*
*--------------------------------------------------------------------------
*/
LEAF(mips3_SetWIRED)
mtc0 a0, MIPS_COP_0_TLB_WIRED
nop # required for 5230
nop # required for 5230
j ra
nop
END(mips3_SetWIRED)
/*--------------------------------------------------------------------------
*
* mips3_GetWIRED --
*
* Get the value from the TLB wired reg.
*
* mips3_GetWIRED(void)
*
* Results:
* Value of wired reg.
*
* Side effects:
* None.
*
*--------------------------------------------------------------------------
*/
LEAF(mips3_GetWIRED)
mfc0 v0, MIPS_COP_0_TLB_WIRED
j ra
nop
END(mips3_GetWIRED)
/*--------------------------------------------------------------------------
*
* mips3_TLBUpdate --
@ -2377,96 +2330,6 @@ LEAF_NOPROFILE(mips3_TBIA)
mtc0 v1, MIPS_COP_0_STATUS # restore status register
END(mips3_TBIA)
LEAF(mips3_read_config)
mfc0 v0, MIPS_COP_0_CONFIG
nop
j ra
nop
END(mips3_read_config)
LEAF(mips3_write_config)
mtc0 a0, MIPS_COP_0_CONFIG
nop
nop
j ra
nop
END(mips3_write_config)
/*----------------------------------------------------------------------------
*
* mips3_cycle_count --
*
* u_int32_t mips3_cycle_count(void)
*
* read 32-bit cycle-counter clock in coprocessor 0.
*
* Results:
* returns 32-bit clock value, incremented automatically by CPU
* at nominal cycle rate (i.e., half the maximum issue rate.)
*
* Side effects:
* none.
*
*----------------------------------------------------------------------------
*/
LEAF(mips3_cycle_count)
mfc0 v0, MIPS_COP_0_COUNT
nop
nop
j ra
nop
END(mips3_cycle_count)
/*--------------------------------------------------------------------------
*
* mips3_write_count --
*
* Write the given value into the Compare reg
*
* mips3_write_count(count)
* int count;
*
* Results:
* None.
*
* Side effects:
*
* Sets the Count value in the CP0 register (9).
*
*--------------------------------------------------------------------------
*/
LEAF(mips3_write_count)
mtc0 a0, MIPS_COP_0_COUNT # Write the Counter value
j ra
nop
END(mips3_write_count)
/*
* Read compare register.
*
* On mips3, generates a hardint 5 interrupt request is generated
* each time the COUNT register increments past the COMPARE register.
*/
LEAF(mips3_read_compare)
mfc0 v0, MIPS_COP_0_COMPARE
nop
j ra
nop
END(mips3_read_compare)
/*
* Write value to compare register.
*
* Side Effects:
* Clears interrupt request from cycle-counter clock.
*/
LEAF(mips3_write_compare)
mtc0 a0, MIPS_COP_0_COMPARE
nop
j ra
nop
END(mips3_write_compare)
LEAF(mips3_FetchIcache)
lw t1, mips_L1ICacheSize
lw t2, mips_L1ICacheLSize
@ -2506,6 +2369,106 @@ LEAF(mips3_FetchDcache)
END(mips3_FetchDcache)
/*
* u_int32_t mips3_cp0_compare_read(void)
*
* Return the current value of the CP0 Compare register.
*/
LEAF(mips3_cp0_compare_read)
mfc0 v0, MIPS_COP_0_COMPARE
j ra
nop
END(mips3_cp0_compare_read)
/*
* void mips3_cp0_compare_write(u_int32_t)
*
* Set the value of the CP0 Compare register.
*/
LEAF(mips3_cp0_compare_write)
mtc0 a0, MIPS_COP_0_COMPARE
nop
nop
j ra
nop
END(mips3_cp0_compare_write)
/*
* u_int32_t mips3_cp0_config_read(void)
*
* Return the current value of the CP0 Config register.
*/
LEAF(mips3_cp0_config_read)
mfc0 v0, MIPS_COP_0_CONFIG
j ra
nop
END(mips3_cp0_config_read)
/*
* void mips3_cp0_config_write(u_int32_t)
*
* Set the value of the CP0 Config register.
*/
LEAF(mips3_cp0_config_write)
mtc0 a0, MIPS_COP_0_CONFIG
nop
nop
j ra
nop
END(mips3_cp0_config_write)
/*
* u_int32_t mips3_cp0_count_read(void)
*
* Return the current value of the CP0 Count register.
*/
LEAF(mips3_cp0_count_read)
mfc0 v0, MIPS_COP_0_COUNT
j ra
nop
END(mips3_cp0_count_read)
/*
* void mips3_cp0_count_write(u_int32_t)
*
* Set the value of the CP0 Count register.
*/
LEAF(mips3_cp0_count_write)
mtc0 a0, MIPS_COP_0_COUNT
nop
nop
j ra
nop
END(mips3_cp0_count_write)
/*
* u_int32_t mips3_cp0_wired_read(void)
*
* Return the current value of the CP0 Wired register.
*/
LEAF(mips3_cp0_wired_read)
mfc0 v0, MIPS_COP_0_TLB_WIRED
j ra
nop
END(mips3_cp0_wired_read)
/*
* void mips3_cp0_wired_write(u_int32_t)
*
* Set the value of the CP0 Wired register.
*/
LEAF(mips3_cp0_wired_write)
mtc0 a0, MIPS_COP_0_TLB_WIRED
nop
nop
j ra
nop
END(mips3_cp0_wired_write)
#if defined(_MIPS_BSD_API) && \
(_MIPS_BSD_API == _MIPS_BSD_API_N32 || _MIPS_BSD_API == _MIPS_BSD_API_LP64)
#error mips3_ld and mips3_sd should be adjusted for N32 or LP64

10
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.106 2000/10/05 01:06:07 cgd Exp $ */
/* $NetBSD: mips_machdep.c,v 1.107 2000/10/05 02:36:45 cgd Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.106 2000/10/05 01:06:07 cgd Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.107 2000/10/05 02:36:45 cgd Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
@ -213,7 +213,7 @@ void
mips3_ConfigCache(mips3_csizebase)
int mips3_csizebase;
{
u_int32_t config = mips3_read_config();
u_int32_t config = mips3_cp0_config_read();
static int snoop_check = 0;
int i;
@ -460,9 +460,9 @@ mips_vector_init()
#endif
#ifdef MIPS3
if (CPUISMIPS3) {
mips3_SetWIRED(0);
mips3_cp0_wired_write(0);
mips3_TBIA(mips_num_tlb_entries);
mips3_SetWIRED(MIPS3_TLB_WIRED_UPAGES);
mips3_cp0_wired_write(MIPS3_TLB_WIRED_UPAGES);
if (mips3_L1TwoWayCache) {
mips3_locore_vec.flushCache = mips3_FlushCache_2way;
mips3_locore_vec.flushDCache = mips3_FlushDCache_2way;

8
sys/arch/pmax/pmax/dec_3min.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: dec_3min.c,v 1.42 2000/06/06 00:08:25 nisimura Exp $ */
/* $NetBSD: dec_3min.c,v 1.43 2000/10/05 02:36:45 cgd Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.42 2000/06/06 00:08:25 nisimura Exp $");
__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.43 2000/10/05 02:36:45 cgd Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -372,7 +372,7 @@ dec_3min_intr(status, cause, pc, ipending)
"r"(ioasic_base + IOASIC_SLOT_8_START));
#ifdef MIPS3
if (CPUISMIPS3) {
latched_cycle_cnt = mips3_cycle_count();
latched_cycle_cnt = mips3_cp0_count_read();
}
#endif
cf.pc = pc;
@ -470,7 +470,7 @@ kn02ba_clkread()
if (CPUISMIPS3) {
u_int32_t mips3_cycles;
mips3_cycles = mips3_cycle_count() - latched_cycle_cnt;
mips3_cycles = mips3_cp0_count_read() - latched_cycle_cnt;
/* XXX divides take 78 cycles: approximate with * 41/2048 */
return((mips3_cycles >> 6) + (mips3_cycles >> 8) +
(mips3_cycles >> 11));

6
sys/arch/sgimips/sgimips/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.2 2000/06/29 15:18:41 soren Exp $ */
/* $NetBSD: cpu.c,v 1.3 2000/10/05 02:36:46 cgd Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@ -69,9 +69,9 @@ cpu_attach(parent, self, aux)
mips_L2CacheSize = 512 * 1024; /* XXX O2 */
#if 1
config = mips3_read_config();
config = mips3_cp0_config_read();
config &= ~MIPS3_CONFIG_SC;
mips3_write_config(config);
mips3_cp0_config_write(config);
#endif
printf(": ");

8
sys/arch/sgimips/sgimips/machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: machdep.c,v 1.5 2000/09/13 15:00:22 thorpej Exp $ */
/* $NetBSD: machdep.c,v 1.6 2000/10/05 02:36:46 cgd Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@ -174,7 +174,7 @@ mach_init(argc, argv, envp)
cpuspeed = strtoul(cpufreq, NULL, 10) / 2; /* XXX MIPS3 only */
#if 0 /* XXX create new mips/mips interface */
mips3_cycle_count = strtoul(cpufreq, NULL, 10) * 5000000;
... something ... = strtoul(cpufreq, NULL, 10) * 5000000;
#endif
uvm_setpagesize();
@ -532,8 +532,8 @@ panic("pcierr: %x %x", *(volatile u_int32_t *)0xbf080004,
if (ipending & MIPS_INT_MASK_5) {
cycles = mips3_cycle_count();
mips3_write_compare(cycles + 900000); /* XXX */
cycles = mips3_cp0_count_read();
mips3_cp0_compare_write(cycles + 900000); /* XXX */
cf.pc = pc;
cf.sr = status;