Rename RM5200 cache ops to mips3_*_2way in anticipation of using them
for other CPUs with 2-way set associative L1 caches as well.
This commit is contained in:
soren
parent
113f160717
commit
5e4ca4defb
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.33 2000/05/23 04:21:40 soren Exp $ */
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/* $NetBSD: locore.h,v 1.34 2000/06/06 17:41:07 soren Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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@ -56,7 +56,7 @@ void mips1_TBIA __P((int));
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void mips1_TBIAP __P((int));
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void mips1_TBIS __P((vaddr_t));
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void mips1_TBRPL __P((vaddr_t, vaddr_t, paddr_t));
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int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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int mips1_TLBUpdate __P((u_int, u_int));
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void mips1_wbflush __P((void));
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void mips1_proc_trampoline __P((void));
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@ -73,23 +73,18 @@ void mips3_TBIA __P((int));
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void mips3_TBIAP __P((int));
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void mips3_TBIS __P((vaddr_t));
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void mips3_TBRPL __P((vaddr_t, vaddr_t, paddr_t));
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int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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int mips3_TLBUpdate __P((u_int, u_int));
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struct tlb;
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void mips3_TLBRead __P((int, struct tlb *));
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#if 0
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void mips3_TLBWriteIndexedVPS __P((u_int index, struct tlb *tlb));
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void mips3_TLBWriteIndexed __P((u_int index, u_int high,
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u_int lo0, u_int lo1));
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#endif
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void mips3_SetWIRED __P((int));
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void mips3_wbflush __P((void));
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void mips3_proc_trampoline __P((void));
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void mips3_cpu_switch_resume __P((void));
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void mips5200_FlushCache __P((void));
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void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len));
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void mips5200_HitFlushDCache __P((vaddr_t, int));
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void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len));
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void mips3_FlushCache_2way __P((void));
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void mips3_FlushDCache_2way __P((vaddr_t addr, vaddr_t len));
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void mips3_HitFlushDCache_2way __P((vaddr_t, int));
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void mips3_FlushICache_2way __P((vaddr_t addr, vaddr_t len));
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u_int32_t mips3_cycle_count __P((void));
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u_int32_t mips3_write_count __P((u_int32_t));
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@ -136,11 +131,11 @@ extern mips_locore_jumpvec_t r4000_locore_vec;
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extern long *mips_locoresw[];
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#if defined(MIPS3) && !defined (MIPS1)
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#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200)
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#define MachFlushCache mips5200_FlushCache
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#define MachFlushDCache mips5200_FlushDCache
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#define MachHitFlushDCache mips5200_HitFlushDCache
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#define MachFlushICache mips5200_FlushICache
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#if defined(MIPS3_5200)
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#define MachFlushCache mips3_FlushCache_2way
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#define MachFlushDCache mips3_FlushDCache_2way
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#define MachHitFlushDCache mips3_HitFlushDCache_2way
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#define MachFlushICache mips3_FlushICache_2way
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#else
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#define MachFlushCache mips3_FlushCache
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#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_mips3.S,v 1.31 2000/05/29 23:40:04 simonb Exp $ */
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/* $NetBSD: locore_mips3.S,v 1.32 2000/06/06 17:41:11 soren Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -104,7 +104,7 @@
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* tlbp -- two integer ops beforehand
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* mtc0 [PageMask,EntryHi,Cp0] -- two integer ops afterwards
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* changing JTLB -- two integer ops afterwards
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* mtc0 [EPC,ErrorEPC,Status] -- two int ops afterwards before eret
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* mtc0 [EPC,ErrorEPC,Status] -- two int ops afterwards before eret
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* config.k0 -- five int ops before kseg0, ckseg0 memref
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*
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* For the IDT R4000, some hazards are:
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@ -116,7 +116,7 @@
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/*
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*============================================================================
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*
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* Mips-III ISA support, part 1: locore exception vectors.
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* MIPS III ISA support, part 1: locore exception vectors.
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* The following code is copied to the vector locations to which
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* the CPU jumps in response to an exception or a TLB miss.
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*
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@ -172,7 +172,7 @@ VECTOR(mips3_TLBMiss, unknown)
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ld k0, 0(k1) # load both 32 bit pte's at once
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3: dsll k1, k0, 34 # Clear soft wired, ro bits
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dsrl k1, k1, 34
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#if BYTE_ORDER == _BIG_ENDIAN
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#if BYTE_ORDER == BIG_ENDIAN
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dmtc0 k1, MIPS_COP_0_TLB_LO1
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dsll k0, k0, 2
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dsrl k0, k0, 34
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@ -1585,7 +1585,7 @@ LEAF(mips3_FlushDCache)
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move t0, a0 # copy start address
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and a0, a0, a2 # get index into primary cache
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addu a1, 127 # Align
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li a2, 0x80000000
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li a2, MIPS_KSEG0_START
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addu a0, a0, a2
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addu a1, a1, a0
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and a0, a0, -128
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@ -1609,7 +1609,7 @@ LEAF(mips3_FlushDCache)
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beq a2, zero, 2f # no secondary cache
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addu a2, -1
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and t0,t0,a2 # secondary cache index
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li a0, 0x80000000
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li a0, MIPS_KSEG0_START
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addu a0, a0, t0 # reduce to kseg0 address
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1:
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cache 3, 0(a0)
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@ -1633,7 +1633,7 @@ END(mips3_FlushDCache)
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* vaddr_t addr, len;
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*
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* Flush data cache for range of addr to addr + len - 1.
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* The address can be any valid viritual address as long
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* The address can be any valid virtual address as long
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* as no TLB invalid traps occur. Only lines with matching
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* addr is flushed.
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*
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@ -1707,13 +1707,9 @@ LEAF(mips3_InvalidateDCache)
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nop
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END(mips3_InvalidateDCache)
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/*----------------------------------------------------------------------------
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*
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* QED R52xx cache flushing code.
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*
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*----------------------------------------------------------------------------
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/*
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* XXX mips/include
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*/
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#define C_ICACHE 0
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#define C_DCACHE 1
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@ -1725,7 +1721,7 @@ END(mips3_InvalidateDCache)
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/*----------------------------------------------------------------------------
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*
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* mips5200_FlushCache -- (QED)
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* mips3_FlushCache_2way --
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*
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* Flush the caches. Assumes a line size of 32 bytes for speed.
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*
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@ -1737,7 +1733,7 @@ END(mips3_InvalidateDCache)
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips5200_FlushCache)
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LEAF(mips3_FlushCache_2way)
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lw t1, mips_L1ICacheSize
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lw t2, mips_L1DCacheSize
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@ -1781,36 +1777,37 @@ LEAF(mips5200_FlushCache)
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bne t0, t1, 1b
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addu t3, t3, 128 # Branch delay slot
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lw t2, mips_L2CacheSize
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beq t2, zero, 2f
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nop
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li t0, MIPS_KSEG0_START
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addu t1, t0, t2
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subu t1, t1, 128
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#if 1
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lw t2, mips_L2CacheSize
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beq t2, zero, 2f
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nop
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li t0, MIPS_KSEG0_START
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addu t1, t0, t2
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subu t1, t1, 128
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1:
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cache 3, 0(t0)
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cache 3, 32(t0)
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cache 3, 64(t0)
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cache 3, 96(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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2:
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j ra
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nop
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END(mips5200_FlushCache)
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cache 3, 0(t0)
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cache 3, 32(t0)
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cache 3, 64(t0)
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cache 3, 96(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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2:
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#endif
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j ra
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nop
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END(mips3_FlushCache_2way)
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/*----------------------------------------------------------------------------
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*
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* mips5200_FlushICache -- (QED)
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* mips3_FlushICache_2way --
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*
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* void mips5200_FlushICache(addr, len)
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* void mips3_FlushICache_2way(addr, len)
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* vaddr_t addr; vsize_t len;
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*
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* Flush instruction cache for range of addr to addr + len - 1.
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* The address can be any valid address so long as no TLB misses occur.
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*
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* Assumes a cache line size of 32 bytes for speed.
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* Does not currently support a second level cache.
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*
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* Addr should be a KSEG0 address, but it can be called with a KUSEG
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* address. To handle flushing both ways here we | in KSEG0 to avoid
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@ -1826,7 +1823,7 @@ END(mips5200_FlushCache)
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips5200_FlushICache)
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LEAF(mips3_FlushICache_2way)
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lw t0, mips_L1ICacheSize
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li t1, MIPS_KSEG0_START
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addu a1, 127 # Align (I $ inval of partials is ok)
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@ -1852,13 +1849,13 @@ LEAF(mips5200_FlushICache)
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j ra
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nop
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END(mips5200_FlushICache)
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END(mips3_FlushICache_2way)
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/*----------------------------------------------------------------------------
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*
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* mips5200_FlushDCache --
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* mips3_FlushDCache_2way --
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*
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* void mips5200_FlushDCache(paddr_t addr, len)
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* void mips3_FlushDCache_2way(paddr_t addr, len)
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*
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* Flush data cache for index range of addr to addr + len - 1.
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* The address is reduced to a kseg0 index.
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@ -1872,7 +1869,7 @@ END(mips5200_FlushICache)
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips5200_FlushDCache)
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LEAF(mips3_FlushDCache_2way)
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lw a2, mips_L1DCacheSize
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srl a3, a2, 1 # two way set associative cache
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addu a2, a3, -1 # offset mask
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@ -1899,21 +1896,19 @@ LEAF(mips5200_FlushDCache)
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bgtz a1, 1b
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addu a3, 128 # Branch delay slot
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/* no s$ support */
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j ra
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nop
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END(mips5200_FlushDCache)
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END(mips3_FlushDCache_2way)
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/*----------------------------------------------------------------------------
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*
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* mips5200_HitFlushDCache -- (QED)
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* mips3_HitFlushDCache_2way --
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*
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* void mips5200_HitFlushDCache(addr, len)
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* void mips3_HitFlushDCache_2way(addr, len)
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* vaddr_t addr, len;
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*
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* Flush data cache for range of addr to addr + len - 1.
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* The address can be any valid viritual address as long
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* The address can be any valid virtual address as long
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* as no TLB invalid traps occur. Only lines with matching
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* addr is flushed.
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*
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@ -1933,7 +1928,7 @@ END(mips5200_FlushDCache)
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips5200_HitFlushDCache)
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LEAF(mips3_HitFlushDCache_2way)
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beq a1, zero, 2f
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addu a1, 31 # Branch delay slot; align length
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and a0, a0, -32
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@ -1943,17 +1938,16 @@ LEAF(mips5200_HitFlushDCache)
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cache C_DCACHE|C_HWBINV,0(a0)
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bne a1, zero, 1b
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addu a0, 32 # Branch delay slot
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2:
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j ra
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nop
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END(mips5200_HitFlushDCache)
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END(mips3_HitFlushDCache_2way)
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/*----------------------------------------------------------------------------
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*
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* mips5200_InvalidateDCache -- (QED)
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* mips3_InvalidateDCache_2way --
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*
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* void mips5200_InvalidateDCache(addr, len)
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* void mips3_InvalidateDCache_2way(addr, len)
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* vaddr_t addr, len;
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*
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* Flush data cache for range of addr to addr + len - 1.
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@ -1973,7 +1967,7 @@ END(mips5200_HitFlushDCache)
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*
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*----------------------------------------------------------------------------
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*/
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LEAF(mips5200_InvalidateDCache)
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LEAF(mips3_InvalidateDCache_2way)
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addu a1, a1, a0 # compute ending address
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1:
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cache C_DCACHE|C_HINV,0(a0)
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@ -1983,7 +1977,7 @@ LEAF(mips5200_InvalidateDCache)
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j ra
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nop
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END(mips5200_InvalidateDCache)
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END(mips3_InvalidateDCache_2way)
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/*----------------------------------------------------------------------------
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*
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@ -2024,7 +2018,7 @@ XLEAF(mips3_VCEI) /* XXXX */
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and k1, 0x00000380 # VIndex[9..7]
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sll k1, k1, 5 # [14..12] <---
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or k0, k0, k1
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or k0, 0x80000000 # physical K0SEG address
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or k0, MIPS_KSEG0_START # physical K0SEG address
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lw k1, _C_LABEL(mips_L2CacheLSize)
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beq k1, zero, 2f # XXX needed?
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subu k1, zero, k1
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