tweak cpu_arch. Eliminate all direct checks of it (making them
use the macro CPUISMIPS3 -- which is badly misnamed), and set it from #defines named CPU_ARCH_N (where N is 1..5, 32, 64).
This commit is contained in:
cgd
parent
a22da181d6
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3f1d3c3066
@ -1,4 +1,4 @@
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/* $NetBSD: cpu.h,v 1.44 2000/08/25 01:04:08 thorpej Exp $ */
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/* $NetBSD: cpu.h,v 1.45 2000/10/05 00:52:59 cgd Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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@ -86,7 +86,17 @@
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#else /* run-time test */
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extern int cpu_arch;
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#define CPUISMIPS3 (cpu_arch >= 3)
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#define CPU_ARCH_MIPS1 (1 << 0)
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#define CPU_ARCH_MIPS2 (1 << 1)
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#define CPU_ARCH_MIPS3 (1 << 2)
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#define CPU_ARCH_MIPS4 (1 << 3)
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#define CPU_ARCH_MIPS5 (1 << 4)
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#define CPU_ARCH_MIPS32 (1 << 5)
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#define CPU_ARCH_MIPS64 (1 << 6)
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/* This test is ... rather bogus */
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#define CPUISMIPS3 ((cpu_arch & (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4)) != 0)
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#endif /* run-time test */
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/*
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.h,v 1.46 2000/10/04 22:44:01 cgd Exp $ */
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/* $NetBSD: locore.h,v 1.47 2000/10/05 00:52:59 cgd Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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@ -218,7 +218,6 @@ typedef int mips_prid_t;
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extern mips_prid_t cpu_id;
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extern mips_prid_t fpu_id;
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extern int cpu_arch;
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extern int mips_num_tlb_entries;
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extern u_int mips_L1DCacheSize;
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extern u_int mips_L1ICacheSize;
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@ -1,4 +1,4 @@
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/* $NetBSD: db_interface.c,v 1.32 2000/08/10 08:01:24 jeffs Exp $ */
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/* $NetBSD: db_interface.c,v 1.33 2000/10/05 00:53:00 cgd Exp $ */
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/*
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* Mach Operating System
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@ -310,11 +310,11 @@ db_write_bytes(addr, size, data)
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kdbpoke_1(p, *(char*)data);
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}
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#ifdef MIPS1
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if (cpu_arch == 1)
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if (!CPUISMIPS3)
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mips1_FlushICache((vaddr_t) addr, size);
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#endif
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#ifdef MIPS3
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if (cpu_arch >= 3) {
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if (CPUISMIPS3) {
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MachHitFlushDCache((vaddr_t) addr, size);
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MachFlushICache((vaddr_t) addr, size);
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}
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@ -330,7 +330,7 @@ db_tlbdump_cmd(addr, have_addr, count, modif)
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char *modif;
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{
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#ifdef MIPS1
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if (cpu_arch == 1) {
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if (!CPUISMIPS3) {
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struct mips1_tlb {
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u_int32_t tlb_hi;
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u_int32_t tlb_lo;
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@ -352,7 +352,7 @@ db_tlbdump_cmd(addr, have_addr, count, modif)
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}
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#endif
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#ifdef MIPS3
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if (cpu_arch >= 3) {
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if (CPUISMIPS3) {
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struct tlb tlb;
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int i;
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@ -1,4 +1,4 @@
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/* $NetBSD: locore.S,v 1.116 2000/10/04 22:44:02 cgd Exp $ */
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/* $NetBSD: locore.S,v 1.117 2000/10/05 00:53:00 cgd Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -1354,13 +1354,10 @@ _C_LABEL(esym):
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.globl _C_LABEL(cpu_id)
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.globl _C_LABEL(fpu_id)
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.globl _C_LABEL(cpu_arch)
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_C_LABEL(cpu_id):
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.word 0
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_C_LABEL(fpu_id):
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.word 0
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_C_LABEL(cpu_arch):
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.word 0
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.globl _C_LABEL(mips_L1DCacheSize)
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.globl _C_LABEL(mips_L1ICacheSize)
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@ -1,4 +1,4 @@
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/* $NetBSD: mips_machdep.c,v 1.104 2000/10/04 21:41:47 cgd Exp $ */
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/* $NetBSD: mips_machdep.c,v 1.105 2000/10/05 00:53:01 cgd Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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@ -52,7 +52,7 @@
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.104 2000/10/04 21:41:47 cgd Exp $");
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__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.105 2000/10/05 00:53:01 cgd Exp $");
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#include "opt_compat_netbsd.h"
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#include "opt_compat_ultrix.h"
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@ -103,6 +103,7 @@ long *mips_locoresw[3];
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extern long *mips1_locoresw[]; /* locore_mips1.S */
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extern long *mips3_locoresw[]; /* locore_mips3.S */
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int cpu_arch;
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int cpu_mhz;
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int mips_num_tlb_entries;
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@ -351,14 +352,14 @@ mips_vector_init()
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#ifdef MIPS1
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case MIPS_R2000:
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case MIPS_R3000:
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cpu_arch = 1;
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cpu_arch = CPU_ARCH_MIPS1;
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mips_num_tlb_entries = MIPS1_TLB_NUM_TLB_ENTRIES;
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mips_L1ICacheSize = mips1_icsize();
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mips_L1DCacheSize = mips1_dcsize();
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break;
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#ifdef ENABLE_MIPS_TX3900
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case MIPS_TX3900:
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cpu_arch = 1;
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cpu_arch = CPU_ARCH_MIPS1;
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switch (MIPS_PRID_REV_MAJ(cpu_id)) {
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default:
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panic("not supported revision");
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@ -383,29 +384,29 @@ mips_vector_init()
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#ifdef MIPS3
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case MIPS_R4000:
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 0;
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break;
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case MIPS_R4100:
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = 32;
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mips3_L1TwoWayCache = 0;
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break;
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case MIPS_R4300:
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = MIPS_R4300_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 0;
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break;
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case MIPS_R4600:
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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/* disable interrupt while cacheflush to workaround the bug */
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break;
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#ifdef ENABLE_MIPS_R4700 /* ID conflict */
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case MIPS_R4700:
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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break;
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@ -414,14 +415,14 @@ mips_vector_init()
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case MIPS_R5000:
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#endif
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case MIPS_RM5200:
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cpu_arch = 4;
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cpu_arch = CPU_ARCH_MIPS4;
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mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
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mips3_L1TwoWayCache = 1;
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break;
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case MIPS_R10000:
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case MIPS_R12000:
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cpu_arch = 4;
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cpu_arch = CPU_ARCH_MIPS4;
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mips_num_tlb_entries = 64;
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mips3_L1TwoWayCache = 1;
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break;
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@ -436,7 +437,7 @@ mips_vector_init()
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* note that the Config register has a non-standard base
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* for IC and DC (2^9 instead of 2^12).
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*/
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cpu_arch = 3;
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cpu_arch = CPU_ARCH_MIPS3;
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mips_num_tlb_entries = 16; /* each entry maps 2 pages */
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mips3_L1TwoWayCache = 1; /* note: line size is 16bytes */
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mips3_csizebase = 0x200; /* non-standard base in Config */
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@ -449,17 +450,15 @@ mips_vector_init()
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cpu_reboot(RB_HALT, NULL);
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}
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switch (cpu_arch) {
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#ifdef MIPS1
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case 1:
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if (!CPUISMIPS3) {
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mips1_TBIA(mips_num_tlb_entries);
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mips1_vector_init();
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memcpy(mips_locoresw, mips1_locoresw, sizeof(mips_locoresw));
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break;
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} else
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#endif
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#ifdef MIPS3
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case 3:
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case 4:
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if (CPUISMIPS3) {
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mips3_SetWIRED(0);
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mips3_TBIA(mips_num_tlb_entries);
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mips3_SetWIRED(MIPS3_TLB_WIRED_UPAGES);
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@ -470,10 +469,11 @@ mips_vector_init()
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}
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mips3_vector_init(mips3_csizebase);
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memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));
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break;
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} else
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#endif
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default:
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printf("MIPS ISA %d: not supported\n", cpu_arch);
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{
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printf("cpu_arch 0x%x: not supported\n", cpu_arch);
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cpu_reboot(RB_HALT, NULL);
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}
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}
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@ -594,7 +594,7 @@ cpu_identify()
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printf("cpu0: ");
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#ifdef MIPS1
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if (cpu_arch == 1) {
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if (!CPUISMIPS3) {
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#ifdef ENABLE_MIPS_TX3900
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printf("%dKB/%dB Instruction %s, %dKB/%dB Data 2-way set associative, %d TLB entries",
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mips_L1ICacheSize / 1024, mips_L1ICacheLSize,
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@ -608,7 +608,7 @@ cpu_identify()
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}
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#endif
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#ifdef MIPS3
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if (cpu_arch >= 3) {
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if (CPUISMIPS3) {
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printf("L1 cache: %dKB/%dB instruction, %dKB/%dB data",
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mips_L1ICacheSize / 1024, mips_L1ICacheLSize,
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mips_L1DCacheSize / 1024, mips_L1DCacheLSize);
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@ -648,7 +648,7 @@ cpu_identify()
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* but printf() doesn't work in it.
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*/
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#if !defined(MIPS3_L2CACHE_ABSENT)
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if (cpu_arch >= 3 && !mips_L2CachePresent) {
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if (CPUISMIPS3 && !mips_L2CachePresent) {
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printf("This kernel doesn't work without L2 cache.\n"
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"Please add \"options MIPS3_L2CACHE_ABSENT\" "
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"to the kernel config file.\n");
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