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Loading the exception return PC in k0 before restoring the status register

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(which disables the interrupts) is *not* a good idea.  k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
This commit is contained in:
mhitch 2000-02-23 17:04:06 +00:00
parent 73f8a2b760
commit e48c624741
1 changed files with 2 additions and 2 deletions
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4
sys/arch/mips/mips/locore_mips1.S
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@ -1,4 +1,4 @@
/* $NetBSD: locore_mips1.S,v 1.21 2000/02/19 01:56:21 mycroft Exp $ */
/* $NetBSD: locore_mips1.S,v 1.22 2000/02/23 17:04:06 mhitch Exp $ */
/*
* Copyright (c) 1992, 1993
@ -244,10 +244,10 @@ NESTED_NOPROFILE(mips1_KernGenException, KERNFRAME_SIZ, ra)
lw a0, TF_BASE+TF_REG_SR(sp)
lw t0, TF_BASE+TF_REG_MULLO(sp)
lw t1, TF_BASE+TF_REG_MULHI(sp)
lw k0, TF_BASE+TF_REG_EPC(sp)
mtc0 a0, MIPS_COP_0_STATUS
mtlo t0
mthi t1
lw k0, TF_BASE+TF_REG_EPC(sp)
lw AT, TF_BASE+TF_REG_AST(sp)
lw v0, TF_BASE+TF_REG_V0(sp)
lw v1, TF_BASE+TF_REG_V1(sp)