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Introduce cpu_intr() whose body is now provided by target ports in 

their own ways.  Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.
This commit is contained in:
nisimura 2000-04-11 02:30:14 +00:00
parent b937447204
commit e342080364
5 changed files with 77 additions and 188 deletions
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3
sys/arch/mips/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.37 2000/03/28 03:11:26 simonb Exp $ */
/* $NetBSD: cpu.h,v 1.38 2000/04/11 02:30:14 nisimura Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -183,6 +183,7 @@ extern struct proc *fpcurproc;
/* trap.c */
void child_return __P((void *));
void netintr __P((void));
int kdbpeek __P((vaddr_t));
/* mips_machdep.c */

45
sys/arch/mips/include/intr.h
View File

@ -1,45 +0,0 @@
/* $NetBSD: intr.h,v 1.2 2000/03/28 02:58:45 simonb Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Jonathan Stone for
* the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MIPS_INTR_H
#define __MIPS_INTR_H
/*
* outcalls from generic mips trap-dispatch code
* to port-specific interrupt and trap handlers.
*/
/* handle i/o device interrupts */
int (*mips_hardware_intr) __P((u_int mask, u_int pc,
u_int statusReg, u_int causeReg));
#endif /* __MIPS_INTR_H */

12
sys/arch/mips/mips/locore_mips1.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips1.S,v 1.27 2000/04/11 01:32:19 nisimura Exp $ */
/* $NetBSD: locore_mips1.S,v 1.28 2000/04/11 02:30:17 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@ -525,7 +525,7 @@ END(mips1_SystemCall)
*
* Handle an interrupt from kernel mode.
* Build kernframe on stack to hold interrupted kernel context, then
* call interrupt() to process it.
* call cpu_intr() to process it.
*
*/
NESTED_NOPROFILE(mips1_KernIntr, KERNFRAME_SIZ, ra)
@ -561,6 +561,7 @@ NESTED_NOPROFILE(mips1_KernIntr, KERNFRAME_SIZ, ra)
sw t9, TF_BASE+TF_REG_T9(sp)
sw ra, TF_BASE+TF_REG_RA(sp)
sw a0, TF_BASE+TF_REG_SR(sp)
and a3, a0, a1 # 4th is STATUS & CAUSE
sw v0, TF_BASE+TF_REG_MULLO(sp)
sw v1, TF_BASE+TF_REG_MULHI(sp)
sw a2, TF_BASE+TF_REG_EPC(sp)
@ -571,7 +572,7 @@ NESTED_NOPROFILE(mips1_KernIntr, KERNFRAME_SIZ, ra)
/*
* Call the interrupt handler.
*/
jal _C_LABEL(interrupt)
jal _C_LABEL(cpu_intr)
nop
/*
* Restore registers and return from the interrupt.
@ -616,7 +617,7 @@ END(mips1_KernIntr)
* kernel stack since there has to be a u page if we came from user mode.
* If there is a pending software interrupt, then save the remaining state
* and call softintr(). This is all because if we call switch() inside
* interrupt(), not all the user registers have been saved in u.u_pcb.
* cpu_intr(), not all the user registers have been saved in u.u_pcb.
*
* Results:
* None.
@ -664,6 +665,7 @@ NESTED_NOPROFILE(mips1_UserIntr, CALLFRAME_SIZ, ra)
sw a0, FRAME_SR(k1)
sw v0, FRAME_MULLO(k1)
sw v1, FRAME_MULHI(k1)
and a3, a0, a1 # 4th is STATUS & CAUSE
sw a2, FRAME_EPC(k1)
addiu sp, k1, -CALLFRAME_SIZ # switch to kernel SP
#ifdef __GP_SUPPORT__
@ -679,7 +681,7 @@ NESTED_NOPROFILE(mips1_UserIntr, CALLFRAME_SIZ, ra)
/*
* Call the interrupt handler.
*/
jal _C_LABEL(interrupt)
jal _C_LABEL(cpu_intr)
mtc0 t0, MIPS_COP_0_STATUS
/*
* Check pending asynchoronous traps.

12
sys/arch/mips/mips/locore_mips3.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore_mips3.S,v 1.19 2000/04/10 04:59:47 nisimura Exp $ */
/* $NetBSD: locore_mips3.S,v 1.20 2000/04/11 02:30:17 nisimura Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@ -753,7 +753,7 @@ END(mips3_SystemCall)
*
* Handle an interrupt from kernel mode.
* Build intrframe on stack to hold interrupted kernel context, then
* call interrupt() to process it.
* call cpu_intr() to process it.
*
*/
NESTED_NOPROFILE(mips3_KernIntr, KERNFRAME_SIZ, ra)
@ -789,6 +789,7 @@ NESTED_NOPROFILE(mips3_KernIntr, KERNFRAME_SIZ, ra)
REG_S t9, TF_BASE+TF_REG_T9(sp)
REG_S ra, TF_BASE+TF_REG_RA(sp)
REG_S a0, TF_BASE+TF_REG_SR(sp)
and a3, a0, a1 # 4th is STATUS & CAUSE
REG_S v0, TF_BASE+TF_REG_MULLO(sp)
REG_S v1, TF_BASE+TF_REG_MULHI(sp)
REG_S a2, TF_BASE+TF_REG_EPC(sp)
@ -800,7 +801,7 @@ NESTED_NOPROFILE(mips3_KernIntr, KERNFRAME_SIZ, ra)
sw ra, KERNFRAME_RA(sp) # for debugging
#endif
mtc0 zero, MIPS_COP_0_STATUS # Reset exl, trap possible.
jal _C_LABEL(interrupt)
jal _C_LABEL(cpu_intr)
nop
/*
* Restore registers and return from the interrupt.
@ -850,7 +851,7 @@ END(mips3_KernIntr)
* kernel stack since there has to be a u page if we came from user mode.
* If there is a pending software interrupt, then save the remaining state
* and call softintr(). This is all because if we call switch() inside
* interrupt(), not all the user registers have been saved in u.u_pcb.
* cpu_intr(), not all the user registers have been saved in u.u_pcb.
*
* Results:
* None.
@ -898,6 +899,7 @@ NESTED_NOPROFILE(mips3_UserIntr, CALLFRAME_SIZ, ra)
REG_S a0, FRAME_SR(k1)
REG_S v0, FRAME_MULLO(k1)
REG_S v1, FRAME_MULHI(k1)
and a3, a0, a1 # 4th is STATUS & CAUSE
REG_S a2, FRAME_EPC(k1)
addiu sp, k1, -CALLFRAME_SIZ # switch to kernel SP
#ifdef __GP_SUPPORT__
@ -917,7 +919,7 @@ NESTED_NOPROFILE(mips3_UserIntr, CALLFRAME_SIZ, ra)
* Call the interrupt handler.
*/
mtc0 t0, MIPS_COP_0_STATUS
jal _C_LABEL(interrupt)
jal _C_LABEL(cpu_intr)
nop
/*
* Restore registers and return from the interrupt.

193
sys/arch/mips/mips/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.124 2000/03/28 03:11:28 simonb Exp $ */
/* $NetBSD: trap.c,v 1.125 2000/04/11 02:30:16 nisimura Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@ -43,7 +43,8 @@
*/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.124 2000/03/28 03:11:28 simonb Exp $");
__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.125 2000/04/11 02:30:16 nisimura Exp $");
#include "opt_cputype.h" /* which mips CPU levels do we support? */
#include "opt_inet.h"
@ -61,14 +62,13 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.124 2000/03/28 03:11:28 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/proc.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/proc.h>
#include <sys/signalvar.h>
#include <sys/syscall.h>
#include <sys/user.h>
#include <sys/buf.h>
#include <sys/reboot.h>
#ifdef KTRACE
#include <sys/ktrace.h>
#endif
@ -89,22 +89,18 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.124 2000/03/28 03:11:28 simonb Exp $");
#include <mips/regnum.h> /* symbolic register indices */
#include <mips/pte.h>
#include <sys/cdefs.h>
#include <sys/syslog.h>
#include <miscfs/procfs/procfs.h>
#ifdef DDB
#include <machine/db_machdep.h>
#include <ddb/db_sym.h>
#endif
/* all this to get prototypes for ipintr() and arpintr() */
#include <sys/socket.h>
#include <net/netisr.h>
#include <net/if.h>
#include <netinet/in.h>
#include <netinet/if_inarp.h>
#include <netinet/ip_var.h>
#ifdef INET
#include <net/route.h>
#include <netinet/in.h>
#include <netinet/ip_var.h>
#include "arp.h"
#if NARP > 0
#include <netinet/if_inarp.h>
#endif
#endif
#ifdef INET6
# ifndef INET
# include <netinet/in.h>
@ -112,26 +108,40 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.124 2000/03/28 03:11:28 simonb Exp $");
#include <netinet/ip6.h>
#include <netinet6/ip6_var.h>
#endif
#ifdef NS
#include <netns/ns_var.h>
#endif
#ifdef ISO
#include <netiso/iso.h>
#include <netiso/clnp.h>
#endif
#ifdef CCITT
#include <netccitt/x25.h>
#include <netccitt/pk.h>
#include <netccitt/pk_extern.h>
#endif
#ifdef NATM
#include <netnatm/natm.h>
#endif
#ifdef NETATALK
#include <netatalk/at_extern.h>
#endif
#include "ppp.h"
#if NPPP > 0
#include <net/ppp_defs.h> /* decls of struct pppstat for.. */
#include <net/if_pppvar.h> /* decl of enum for... */
#include <net/if_ppp.h> /* pppintr() prototype */
#include <net/ppp_defs.h>
#include <net/if_ppp.h>
#endif
/*
* Port-specific hardware interrupt handler
*/
#ifdef DDB
#include <machine/db_machdep.h>
#include <ddb/db_sym.h>
#endif
int astpending;
int want_resched;
unsigned ssir;
int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned)) = 0;
void (*mips_software_intr) __P((int)) = 0;
int softisr; /* for extensible software interrupt framework */
int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned)) = 0;
#if defined(MIPS3) && defined(MIPS3_INTERNAL_TIMER_INTERRUPT)
u_int32_t mips3_intr_cycle_count;
@ -179,15 +189,12 @@ void syscall __P((unsigned, unsigned, unsigned));
void interrupt __P((unsigned, unsigned, unsigned));
void ast __P((unsigned));
void dealfpu __P((unsigned, unsigned, unsigned));
void netintr __P((void));
extern void softserial __P((void));
void MachEmulateFP __P((unsigned));
void MachFPInterrupt __P((unsigned, unsigned, unsigned,
struct frame *));
/*
* Other forward declarations.
*/
vaddr_t MachEmulateBranch __P((struct frame *, vaddr_t, unsigned, int));
extern void MachEmulateFP __P((unsigned));
extern void MachFPInterrupt __P((unsigned, unsigned, unsigned, struct frame *));
void
userret(p, pc, sticks)
@ -363,7 +370,6 @@ syscall(status, cause, opc)
/*
* fork syscall returns directly to user process via proc_trampoline,
* which will be called the very first time when child gets running.
* no more FORK_BRAINDAMAGED.
*/
void
child_return(arg)
@ -407,7 +413,8 @@ trap(status, cause, vaddr, opc, frame)
u_quad_t sticks = 0;
struct proc *p = curproc;
vm_prot_t ftype;
void fswintrberr __P((void));
extern struct proc *fpcurproc;
extern void fswintrberr __P((void));
uvmexp.traps++;
type = TRAPTYPE(cause);
@ -715,104 +722,23 @@ trap(status, cause, vaddr, opc, frame)
return;
}
#include <net/netisr.h>
#include "arp.h"
#include "ppp.h"
#ifdef NS
#include <netns/ns_var.h>
#endif
#ifdef ISO
#include <netiso/iso.h>
#include <netiso/clnp.h>
#endif
#ifdef CCITT
#include <netccitt/x25.h>
#include <netccitt/pk.h>
#include <netccitt/pk_extern.h>
#endif
#ifdef NATM
#include <netnatm/natm.h>
#endif
#ifdef NETATALK
#include <netatalk/at_extern.h>
#endif
/*
* Handle an interrupt.
* N.B., curproc might be NULL.
*/
void
interrupt(status, cause, pc)
unsigned status;
unsigned cause;
unsigned pc;
netintr()
{
unsigned mask;
#define DONETISR(bit, fn) \
do { \
if (n & (1 << bit)) \
fn(); \
} while (0)
mask = cause & status; /* pending interrupts & enable mask */
int n;
n = netisr; netisr = 0;
#if defined(MIPS3) && defined(MIPS_INT_MASK_CLOCK)
if ((mask & MIPS_INT_MASK_CLOCK) && CPUISMIPS3) {
mips3_intr_cycle_count = mips3_cycle_count();
/*
* Writing a value to the Compare register,
* as a side effect, clears the timer interrupt request.
*/
mips3_write_compare(mips3_intr_cycle_count + mips3_timer_delta);
}
#endif
uvmexp.intrs++;
/* real device interrupt */
if ((mask & INT_MASK_REAL_DEV) && mips_hardware_intr) {
_splset((*mips_hardware_intr)(mask, pc, status, cause));
}
#ifdef INT_MASK_FPU_DEAL
if (mask & INT_MASK_FPU_DEAL) {
intrcnt[FPU_INTR]++;
if (!USERMODE(status))
panic("kernel used FPU: PC %x, CR %x, SR %x",
pc, cause, status);
/* dealfpu(status, cause, pc); */
MachFPInterrupt(status, cause, pc, curproc->p_md.md_regs);
}
#endif
/* simulated interrupt */
if ((mask & MIPS_SOFT_INT_MASK_1)
|| ((netisr|softisr) && (status & MIPS_SOFT_INT_MASK_1))) {
int isr, sisr;
isr = netisr; netisr = 0;
sisr = softisr; softisr = 0;
clearsoftnet();
uvmexp.softs++;
if (isr) {
intrcnt[SOFTNET_INTR]++;
#define DONETISR(bit, fn) do { \
if (isr & (1 << bit)) \
fn(); \
} while (0)
intrcnt[SOFTNET_INTR]++;
#include <net/netisr_dispatch.h>
#undef DONETISR
}
if (sisr && mips_software_intr)
(*mips_software_intr)(sisr);
}
/* 'softclock' interrupt */
if (mask & MIPS_SOFT_INT_MASK_0) {
clearsoftclock();
uvmexp.softs++;
intrcnt[SOFTCLOCK_INTR]++;
softclock();
}
}
/*
@ -1084,6 +1010,8 @@ mips_singlestep(p)
#if defined(DEBUG) || defined(DDB)
mips_reg_t kdbrpeek __P((vaddr_t));
extern void stacktrace __P((void)); /*XXX*/
extern void logstacktrace __P((void)); /*XXX*/
int
@ -1135,7 +1063,9 @@ extern char mips3_UserGenException[];
extern char mips3_KernIntr[];
extern char mips3_UserIntr[];
extern char mips3_SystemCall[];
int main __P((void*));
extern int main __P((void*));
extern void mips_idle __P((void));
extern void cpu_switch __P((struct proc *));
/*
* stack trace code, also useful to DDB one day
@ -1418,7 +1348,6 @@ static struct { void *addr; char *name;} names[] = {
Name(stacktrace),
Name(stacktrace_subr),
Name(main),
Name(interrupt),
Name(trap),
#ifdef MIPS1 /* r2000 family (mips-I cpu) */