put cache op #defines up at the top of the file, so all cache ops can
use them. Rename them to match the names in See Mips Run; they're not as orthogonal as values or'd together might make you think... Finally, actually use them for every bloody cache op.
This commit is contained in:
cgd
parent
66db4224da
commit
79d0534b05
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@ -1,4 +1,4 @@
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/* $NetBSD: locore_mips3.S,v 1.34 2000/06/09 06:07:01 soda Exp $ */
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/* $NetBSD: locore_mips3.S,v 1.35 2000/06/17 01:35:28 cgd Exp $ */
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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@ -113,6 +113,30 @@
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* Obvious solution is to take least common denominator.
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*/
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/*
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* XXX mips/include
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*/
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#define C_IINV_I 0x00
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#define C_IWBINV_D 0x01
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#define C_IINV_SI 0x02
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#define C_IWBINV_SD 0x03
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#define C_ILDTAG_I 0x04
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#define C_ILDTAG_D 0x05
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#define C_ILDTAG_SI 0x06
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#define C_ILDTAG_SD 0x07
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#define C_HINV_I 0x10
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#define C_HINV_D 0x11
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#define C_HINV_SI 0x12
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#define C_HINV_SD 0x13
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#define C_HWBINV_D 0x15
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#define C_HWBINV_SD 0x17
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#define C_HSETV_SI 0x1e
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#define C_HSETV_SD 0x1f
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/*
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*============================================================================
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*
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@ -1473,14 +1497,14 @@ LEAF(mips3_FlushCache)
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addu t1, t0, t1 # End address
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subu t1, t1, 128
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1:
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cache 0, 0(t0)
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cache 0, 16(t0)
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cache 0, 32(t0)
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cache 0, 48(t0)
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cache 0, 64(t0)
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cache 0, 80(t0)
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cache 0, 96(t0)
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cache 0, 112(t0)
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cache C_IINV_I, 0(t0)
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cache C_IINV_I, 16(t0)
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cache C_IINV_I, 32(t0)
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cache C_IINV_I, 48(t0)
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cache C_IINV_I, 64(t0)
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cache C_IINV_I, 80(t0)
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cache C_IINV_I, 96(t0)
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cache C_IINV_I, 112(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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@ -1491,14 +1515,14 @@ LEAF(mips3_FlushCache)
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addu t1, t0, t2 # End address
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subu t1, t1, 128
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1:
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cache 1, 0(t0)
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cache 1, 16(t0)
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cache 1, 32(t0)
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cache 1, 48(t0)
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cache 1, 64(t0)
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cache 1, 80(t0)
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cache 1, 96(t0)
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cache 1, 112(t0)
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cache C_IWBINV_D, 0(t0)
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cache C_IWBINV_D, 16(t0)
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cache C_IWBINV_D, 32(t0)
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cache C_IWBINV_D, 48(t0)
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cache C_IWBINV_D, 64(t0)
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cache C_IWBINV_D, 80(t0)
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cache C_IWBINV_D, 96(t0)
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cache C_IWBINV_D, 112(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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@ -1509,10 +1533,10 @@ LEAF(mips3_FlushCache)
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addu t1, t0, t2
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subu t1, t1, 128
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1:
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cache 3, 0(t0)
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cache 3, 32(t0)
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cache 3, 64(t0)
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cache 3, 96(t0)
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cache C_IWBINV_SD, 0(t0)
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cache C_IWBINV_SD, 32(t0)
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cache C_IWBINV_SD, 64(t0)
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cache C_IWBINV_SD, 96(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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2:
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@ -1544,14 +1568,14 @@ LEAF(mips3_FlushICache)
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addu a1, 127 # Align
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srl a1, a1, 7 # Number of unrolled loops
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1:
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cache 0, 0(a0)
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cache 0, 16(a0)
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cache 0, 32(a0)
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cache 0, 48(a0)
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cache 0, 64(a0)
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cache 0, 80(a0)
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cache 0, 96(a0)
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cache 0, 112(a0)
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cache C_IINV_I, 0(a0)
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cache C_IINV_I, 16(a0)
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cache C_IINV_I, 32(a0)
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cache C_IINV_I, 48(a0)
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cache C_IINV_I, 64(a0)
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cache C_IINV_I, 80(a0)
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cache C_IINV_I, 96(a0)
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cache C_IINV_I, 112(a0)
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addu a1, -1
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bne a1, zero, 1b
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addu a0, 128
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@ -1593,14 +1617,14 @@ LEAF(mips3_FlushDCache)
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srl a1, a1, 7 # Compute number of cache lines
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move t1, a1 # copy length
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1:
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cache 1, 0(a0)
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cache 1, 16(a0)
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cache 1, 32(a0)
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cache 1, 48(a0)
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cache 1, 64(a0)
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cache 1, 80(a0)
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cache 1, 96(a0)
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cache 1, 112(a0)
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cache C_IWBINV_D, 0(a0)
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cache C_IWBINV_D, 16(a0)
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cache C_IWBINV_D, 32(a0)
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cache C_IWBINV_D, 48(a0)
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cache C_IWBINV_D, 64(a0)
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cache C_IWBINV_D, 80(a0)
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cache C_IWBINV_D, 96(a0)
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cache C_IWBINV_D, 112(a0)
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addu a1, -1
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bne a1, zero, 1b
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addu a0, 128
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@ -1612,10 +1636,10 @@ LEAF(mips3_FlushDCache)
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li a0, MIPS_KSEG0_START
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addu a0, a0, t0 # reduce to kseg0 address
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1:
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cache 3, 0(a0)
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cache 3, 32(a0)
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cache 3, 64(a0)
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cache 3, 96(a0)
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cache C_IWBINV_SD, 0(a0)
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cache C_IWBINV_SD, 32(a0)
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cache C_IWBINV_SD, 64(a0)
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cache C_IWBINV_SD, 96(a0)
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addu t1, -1
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bne t1, zero, 1b
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addu a0, 128
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@ -1654,19 +1678,19 @@ LEAF(mips3_HitFlushDCache)
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subu a1, a1, a0
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srl a1, a1, 7 # Compute number of cache lines
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1:
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cache 0x15, 0(a0)
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cache 0x15, 16(a0)
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cache 0x15, 32(a0)
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cache 0x15, 48(a0)
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cache 0x15, 64(a0)
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cache 0x15, 80(a0)
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cache 0x15, 96(a0)
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cache 0x15, 112(a0)
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cache C_HWBINV_D, 0(a0)
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cache C_HWBINV_D, 16(a0)
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cache C_HWBINV_D, 32(a0)
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cache C_HWBINV_D, 48(a0)
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cache C_HWBINV_D, 64(a0)
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cache C_HWBINV_D, 80(a0)
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cache C_HWBINV_D, 96(a0)
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cache C_HWBINV_D, 112(a0)
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#if 1
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cache 0x17, 0(a0)
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cache 0x17, 32(a0)
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cache 0x17, 64(a0)
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cache 0x17, 96(a0)
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cache C_HWBINV_SD, 0(a0)
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cache C_HWBINV_SD, 32(a0)
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cache C_HWBINV_SD, 64(a0)
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cache C_HWBINV_SD, 96(a0)
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#endif
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addu a1, -1
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bne a1, zero, 1b
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@ -1698,27 +1722,15 @@ END(mips3_HitFlushDCache)
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LEAF(mips3_InvalidateDCache)
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addu a1, a1, a0 # compute ending address
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1:
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cache 0x13, 0(a0)
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cache C_HINV_SD, 0(a0)
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addu a0, a0, 4
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bne a0, a1, 1b
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cache 0x11,-4(a0)
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cache C_HINV_D,-4(a0)
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j ra
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nop
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END(mips3_InvalidateDCache)
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/*
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* XXX mips/include
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*/
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#define C_ICACHE 0
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#define C_DCACHE 1
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#define C_IINV (0 << 2)
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#define C_IWBINV (0 << 2)
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#define C_HINV (4 << 2)
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#define C_HWBINV (5 << 2)
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#define C_HWB (6 << 2)
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/*----------------------------------------------------------------------------
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*
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* mips3_FlushCache_2way --
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@ -1745,15 +1757,15 @@ LEAF(mips3_FlushCache_2way)
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or t3, t1, t0 # Second way address
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addu t1, t0, t1 # End address
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1:
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cache C_ICACHE|C_IINV, 0(t0)
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cache C_ICACHE|C_IINV, 0(t3)
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cache C_ICACHE|C_IINV, 32(t0)
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cache C_ICACHE|C_IINV, 32(t3)
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cache C_ICACHE|C_IINV, 64(t0)
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cache C_ICACHE|C_IINV, 64(t3)
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cache C_ICACHE|C_IINV, 96(t0)
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cache C_IINV_I, 0(t0)
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cache C_IINV_I, 0(t3)
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cache C_IINV_I, 32(t0)
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cache C_IINV_I, 32(t3)
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cache C_IINV_I, 64(t0)
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cache C_IINV_I, 64(t3)
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cache C_IINV_I, 96(t0)
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addu t0, t0, 128
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cache C_ICACHE|C_IINV, 96(t3)
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cache C_IINV_I, 96(t3)
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bne t0, t1, 1b
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addu t3, t3, 128 # Branch delay slot
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@ -1765,15 +1777,15 @@ LEAF(mips3_FlushCache_2way)
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or t3, t2, t0 # Second way address
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addu t1, t0, t2 # End address
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1:
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cache C_DCACHE|C_IWBINV, 0(t0)
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cache C_DCACHE|C_IWBINV, 0(t3)
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cache C_DCACHE|C_IWBINV, 32(t0)
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cache C_DCACHE|C_IWBINV, 32(t3)
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cache C_DCACHE|C_IWBINV, 64(t0)
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cache C_DCACHE|C_IWBINV, 64(t3)
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cache C_DCACHE|C_IWBINV, 96(t0)
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cache C_IWBINV_D, 0(t0)
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cache C_IWBINV_D, 0(t3)
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cache C_IWBINV_D, 32(t0)
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cache C_IWBINV_D, 32(t3)
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cache C_IWBINV_D, 64(t0)
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cache C_IWBINV_D, 64(t3)
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cache C_IWBINV_D, 96(t0)
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addu t0, t0, 128
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cache C_DCACHE|C_IWBINV, 96(t3)
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cache C_IWBINV_D, 96(t3)
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bne t0, t1, 1b
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addu t3, t3, 128 # Branch delay slot
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@ -1785,10 +1797,10 @@ LEAF(mips3_FlushCache_2way)
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addu t1, t0, t2
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subu t1, t1, 128
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1:
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cache 3, 0(t0)
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cache 3, 32(t0)
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cache 3, 64(t0)
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cache 3, 96(t0)
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cache C_IWBINV_SD, 0(t0)
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cache C_IWBINV_SD, 32(t0)
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cache C_IWBINV_SD, 64(t0)
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cache C_IWBINV_SD, 96(t0)
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bne t0, t1, 1b
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addu t0, t0, 128
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2:
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@ -1834,16 +1846,16 @@ LEAF(mips3_FlushICache_2way)
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srl a1, a1, 7 # Number of unrolled loops
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or t0, t0, a0 # Way 1 index offset.
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1:
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cache C_ICACHE|C_IINV, 0(a0)
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cache C_ICACHE|C_IINV, 0(t0) # other way
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cache C_ICACHE|C_IINV, 32(a0)
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cache C_ICACHE|C_IINV, 32(t0) # other way
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cache C_IINV_I, 0(a0)
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cache C_IINV_I, 0(t0) # other way
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cache C_IINV_I, 32(a0)
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cache C_IINV_I, 32(t0) # other way
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addu a1, -1
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cache C_ICACHE|C_IINV, 64(a0)
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cache C_ICACHE|C_IINV, 64(t0) # other way
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cache C_ICACHE|C_IINV, 96(a0)
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cache C_IINV_I, 64(a0)
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cache C_IINV_I, 64(t0) # other way
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cache C_IINV_I, 96(a0)
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addu a0, 128
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cache C_ICACHE|C_IINV, 96(t0) # other way
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cache C_IINV_I, 96(t0) # other way
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bgt a1, zero, 1b
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addu t0, 128 # Branch delay slot
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@ -1883,15 +1895,15 @@ LEAF(mips3_FlushDCache_2way)
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addu a3, a0, a3 # second set of two way cache
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srl a1, a1, 7 # Compute number of cache blocks
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1:
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cache C_DCACHE|C_IWBINV, 0(a0)
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cache C_DCACHE|C_IWBINV, 0(a3) # second way
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cache C_DCACHE|C_IWBINV, 32(a0)
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cache C_DCACHE|C_IWBINV, 32(a3)
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cache C_IWBINV_D, 0(a0)
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cache C_IWBINV_D, 0(a3) # second way
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cache C_IWBINV_D, 32(a0)
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cache C_IWBINV_D, 32(a3)
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addu a1, -1
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cache C_DCACHE|C_IWBINV, 64(a0)
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cache C_DCACHE|C_IWBINV, 64(a3)
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cache C_DCACHE|C_IWBINV, 96(a0)
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cache C_DCACHE|C_IWBINV, 96(a3)
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cache C_IWBINV_D, 64(a0)
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cache C_IWBINV_D, 64(a3)
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cache C_IWBINV_D, 96(a0)
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cache C_IWBINV_D, 96(a3)
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addu a0, 128
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bgtz a1, 1b
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addu a3, 128 # Branch delay slot
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@ -1935,7 +1947,7 @@ LEAF(mips3_HitFlushDCache_2way)
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srl a1, a1, 5 # Compute number of cache lines
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1:
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addu a1, -1
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cache C_DCACHE|C_HWBINV,0(a0)
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cache C_HWBINV_D,0(a0)
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bne a1, zero, 1b
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addu a0, 32 # Branch delay slot
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2:
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@ -1970,7 +1982,7 @@ END(mips3_HitFlushDCache_2way)
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LEAF(mips3_InvalidateDCache_2way)
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addu a1, a1, a0 # compute ending address
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1:
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cache C_DCACHE|C_HINV,0(a0)
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cache C_HINV_D,0(a0)
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addu a0, a0, 32
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bltu a0, a1, 1b
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nop # Branch delay slot
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@ -2009,10 +2021,10 @@ XLEAF(mips3_VCEI) /* XXXX */
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nop
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and k0, -16
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sw k0, vce_savek0 # save virtual address
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cache 1, 0(k0) # writeback primary line
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cache C_IWBINV_D, 0(k0) # writeback primary line
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nop
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nop
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cache 7, 0(k0) # read L2Cache tag
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cache C_ILDTAG_SD, 0(k0) # read L2Cache tag
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and k0, PGOFSET
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mfc0 k1, MIPS_COP_0_TAG_LO
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and k1, 0x00000380 # VIndex[9..7]
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@ -2024,14 +2036,14 @@ XLEAF(mips3_VCEI) /* XXXX */
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subu k1, zero, k1
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and k0, k0, k1 # align to L2CacheLSize
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1:
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cache 1, 0(k0) # flush 32 bytes
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cache 1, 16(k0)
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cache C_IWBINV_D, 0(k0) # flush 32 bytes
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cache C_IWBINV_D, 16(k0)
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addu k1, 32
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bltz k1, 1b
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addu k0, 32
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2:
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lw k0, vce_savek0 # get original address
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cache 31, 0(k0)
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cache C_HSETV_SD, 0(k0)
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nop
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#ifdef DEBUG
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mfc0 k1, MIPS_COP_0_EXC_PC
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@ -2555,7 +2567,7 @@ LEAF(mips3_FetchIcache)
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li t0, MIPS_KSEG0_START
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addu t3, t1, t0
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1:
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cache 4, 0(t0)
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cache C_ILDTAG_I, 0(t0)
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mfc0 t4, MIPS_COP_0_TAG_LO
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sw t4, 0(a0)
|
||||
addu a0, 4
|
||||
|
|
@ -2574,7 +2586,7 @@ LEAF(mips3_FetchDcache)
|
|||
li t0, MIPS_KSEG0_START
|
||||
addu t3, t1, t0
|
||||
1:
|
||||
cache 5, 0(t0)
|
||||
cache C_ILDTAG_D, 0(t0)
|
||||
mfc0 t4, MIPS_COP_0_TAG_LO
|
||||
sw t4, 0(a0)
|
||||
addu a0, 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue