- Fix a bug in mips1_TBIAP() misbehaving like as mips1_TBIA().
- Adjust comments to reflect what it does.
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nisimura
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98359af3d1
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53e7a8c8d5
@ -1,4 +1,4 @@
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/* $NetBSD: locore_mips1.S,v 1.25 2000/04/10 04:59:47 nisimura Exp $ */
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/* $NetBSD: locore_mips1.S,v 1.26 2000/04/10 11:38:16 nisimura Exp $ */
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/*
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* Copyright (c) 1992, 1993
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@ -1038,33 +1038,6 @@ LEAF(mips1_TLBFlushPID)
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END(mips1_TLBFlushPID)
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#endif
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/*
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* void mips1_TBIS(vaddr_t va)
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*
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* Invalidate a TLB entry for given virtual address if found in TLB.
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*/
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LEAF(mips1_TBIS)
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mfc0 v1, MIPS_COP_0_STATUS # Save the status register.
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mtc0 zero, MIPS_COP_0_STATUS # Disable interrupts
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mfc0 t0, MIPS_COP_0_TLB_HI # Get current PID
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nop
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mtc0 a0, MIPS_COP_0_TLB_HI # look for addr & PID
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nop
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tlbp # Probe for the entry.
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mfc0 v0, MIPS_COP_0_TLB_INDEX # See what we got
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li t1, MIPS_KSEG0_START # Load invalid entry.
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bltz v0, 1f # index < 0 => !found
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mtc0 t1, MIPS_COP_0_TLB_HI # Mark entry high as invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # Zero out low entry.
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nop
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tlbwi
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1:
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mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
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j ra
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mtc0 v1, MIPS_COP_0_STATUS # Restore the status register
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END(mips1_TBIS)
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/*--------------------------------------------------------------------------
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*
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* mips1_TLBUpdate --
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@ -1760,9 +1733,9 @@ END(mips1_proc_trampoline)
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/*
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* void mips1_cpu_switch_resume(struct proc *newproc)
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*
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* Wiredown the USPACE of newproc with TLB entry#0. Check
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* whether target USPACE is already refered by some TLB entry(s)
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* before that, and make sure TBIS(them) in the case.
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* Wiredown the USPACE of newproc with TLB entry#0 and #1. Check
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* if target USPACE is already refered by any TLB entry before
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* doing that, and make sure TBIS(them) in the case.
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*/
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LEAF_NOPROFILE(mips1_cpu_switch_resume)
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lw a1, P_MD_UPTE_0(a0) # a1 = upte[0]
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@ -1819,11 +1792,38 @@ resume:
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nop
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END(mips1_cpu_switch_resume)
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/*
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* void mips1_TBIS(vaddr_t va)
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*
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* Invalidate a TLB entry for given virtual address if found in TLB.
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*/
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LEAF(mips1_TBIS)
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mfc0 v1, MIPS_COP_0_STATUS # save status register
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mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
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mfc0 t0, MIPS_COP_0_TLB_HI # save current PID
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nop
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mtc0 a0, MIPS_COP_0_TLB_HI # look for addr & PID
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nop
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tlbp # probe the entry in question
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mfc0 a0, MIPS_COP_0_TLB_INDEX # see what we got
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li t1, MIPS_KSEG0_START # load invalid address
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bltz a0, 1f # index < 0 then skip
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mtc0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # zero out entryLo
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nop
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tlbwi
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1:
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mtc0 t0, MIPS_COP_0_TLB_HI # restore PID
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j ra
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mtc0 v1, MIPS_COP_0_STATUS # restore the status register
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END(mips1_TBIS)
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/*
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* void mips1_TBIAP(int sizeofTLB)
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*
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* Invalidate TLB entries belong to per process user spaces while
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* retaining entries for kernel space marked global.
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* leaving entries for kernel space marked global intact.
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*/
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LEAF(mips1_TBIAP)
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mfc0 v1, MIPS_COP_0_STATUS # save status register
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@ -1831,19 +1831,20 @@ LEAF(mips1_TBIAP)
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li t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
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sll t2, a0, MIPS1_TLB_INDEX_SHIFT
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li v0, MIPS_KSEG0_START
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li v0, MIPS_KSEG0_START # invalid address
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# Align the starting value (t1) and the upper bound (t2)
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# do {} while (t1 < t2)
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1:
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mtc0 t1, MIPS_COP_0_TLB_INDEX # set index
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nop
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tlbr # obtain an entry
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mfc0 t0, MIPS_COP_0_TLB_LOW
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mfc0 a0, MIPS_COP_0_TLB_LOW
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nop
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andi t0, v0, MIPS1_PG_G # check PG_G bit
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bnez t0, 2f
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mtc0 v0, MIPS_COP_0_TLB_HI # mark entryhi as invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # zero out entrylo
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andi a0, a0, MIPS1_PG_G # check to see it has G bit
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bnez a0, 2f
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nop
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mtc0 v0, MIPS_COP_0_TLB_HI # make entryHi invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # zero out entryLo
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nop
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tlbwi # invalidate the TLB entry
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2:
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@ -1851,9 +1852,9 @@ LEAF(mips1_TBIAP)
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bne t1, t2, 1b
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nop
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j ra # new TLBPID will be set soon
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j ra # new TLBpid will be set soon
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mtc0 v1, MIPS_COP_0_STATUS # restore status register
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END(mips1_TBIAP)
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END(mips1_TBIAP)
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/*
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* void mips1_TBIA(int sizeofTLB)
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@ -1865,21 +1866,22 @@ LEAF(mips1_TBIA)
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mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
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li t1, MIPS_KSEG0_START
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mtc0 t1, MIPS_COP_0_TLB_HI # mark entryhi as invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # zero out entrylo
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mtc0 t1, MIPS_COP_0_TLB_HI # make entryHi invalid
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mtc0 zero, MIPS_COP_0_TLB_LOW # zero out entryLo
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# Align the starting value (t1) and the upper bound (t2).
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move t1, zero
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sll t2, a0, MIPS1_TLB_INDEX_SHIFT
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sll a0, a0, MIPS1_TLB_INDEX_SHIFT
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# do {} while (t1 < a0)
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1:
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mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLB index
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mtc0 t1, MIPS_COP_0_TLB_INDEX # set TLBindex
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addu t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT # increment index
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bne t1, t2, 1b
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tlbwi # invalidate the TLB entry
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bne t1, a0, 1b
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tlbwi # invalidate the entry
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j ra
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mtc0 v1, MIPS_COP_0_STATUS # restore status register
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END(mips1_TBIA)
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END(mips1_TBIA)
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.data
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mips1_excausesw:
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