Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2,
and rename it to MIPS3_TLB_WIRED_UPAGES. The value of wired register becomes variable on arc port, and arc is the only mips3 port which uses the wired TLB entries 2..7.
This commit is contained in:
soda
parent
d875086bb3
commit
2047c95e49
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: machdep.c,v 1.37 2000/06/09 05:41:58 soda Exp $ */
|
||||
/* $NetBSD: machdep.c,v 1.38 2000/06/09 06:06:57 soda Exp $ */
|
||||
/* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -261,8 +261,6 @@ mach_init(argc, argv, envv)
|
|||
&mem_cluster_cnt);
|
||||
}
|
||||
|
||||
arc_init_wired_map();
|
||||
|
||||
/*
|
||||
* Get config register now as mapped from BIOS since we are
|
||||
* going to demap these addresses later. We want as may TLB
|
||||
|
|
@ -569,6 +567,9 @@ mach_init(argc, argv, envv)
|
|||
*
|
||||
* XXX - reserve these KVA space after UVM initialization.
|
||||
*/
|
||||
|
||||
arc_init_wired_map();
|
||||
|
||||
switch (cputype) {
|
||||
case ACER_PICA_61:
|
||||
case MAGNUM:
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: wired_map.c,v 1.2 2000/06/09 05:51:52 soda Exp $ */
|
||||
/* $NetBSD: wired_map.c,v 1.3 2000/06/09 06:06:58 soda Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (C) 2000 Shuichiro URATA. All rights reserved.
|
||||
|
|
@ -30,17 +30,16 @@
|
|||
#include <sys/systm.h>
|
||||
#include <vm/vm.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <mips/locore.h>
|
||||
#include <mips/pte.h>
|
||||
#include <arc/arc/wired_map.h>
|
||||
|
||||
#define MIPS3_PG_SIZE_MASK_TO_SIZE(sizemask) \
|
||||
((((sizemask) | 0x00001fff) + 1) / 2)
|
||||
#define MIPS3_LOCORE_TLB_WIRED_ENTRIES 2
|
||||
|
||||
#define VA_FREE_START 0xe0000000 /* XXX */
|
||||
|
||||
#define ARC_TLB_WIRED_ENTRIES \
|
||||
(MIPS3_TLB_WIRED_ENTRIES - MIPS3_LOCORE_TLB_WIRED_ENTRIES)
|
||||
#define ARC_TLB_WIRED_ENTRIES 8 /* upper limit */
|
||||
#define ARC_WIRED_PG_MASK MIPS3_PG_SIZE_16M
|
||||
#define ARC_WIRED_PAGE_SIZE MIPS3_PG_SIZE_MASK_TO_SIZE(ARC_WIRED_PG_MASK)
|
||||
#define ARC_WIRED_ENTRY_SIZE (ARC_WIRED_PAGE_SIZE * 2)
|
||||
|
|
@ -85,6 +84,10 @@ arc_enter_wired(va, pa0, pa1, pg_size)
|
|||
wired_map[nwired].pa1 = pa1;
|
||||
wired_map[nwired].size = MIPS3_PG_SIZE_MASK_TO_SIZE(pg_size);
|
||||
|
||||
/* Allocate new wired entry */
|
||||
mips3_SetWIRED(MIPS3_TLB_WIRED_UPAGES + nwired + 1);
|
||||
|
||||
/* Map to it */
|
||||
tlb.tlb_mask = pg_size;
|
||||
tlb.tlb_hi = mips3_vad_to_vpn(va);
|
||||
if (pa0 == 0)
|
||||
|
|
@ -95,7 +98,7 @@ arc_enter_wired(va, pa0, pa1, pg_size)
|
|||
tlb.tlb_lo1 = MIPS3_PG_G;
|
||||
else
|
||||
tlb.tlb_lo1 = mips3_paddr_to_tlbpfn(pa1) | MIPS3_PG_IOPAGE;
|
||||
mips3_TLBWriteIndexedVPS(MIPS3_LOCORE_TLB_WIRED_ENTRIES + nwired,
|
||||
mips3_TLBWriteIndexedVPS(MIPS3_TLB_WIRED_UPAGES + nwired,
|
||||
&tlb);
|
||||
|
||||
if (va_free < va + wired_map[nwired].size * 2) {
|
||||
|
|
@ -111,7 +114,7 @@ arc_wired_map_paddr_entry(pa, vap, sizep)
|
|||
vaddr_t *vap;
|
||||
vsize_t *sizep;
|
||||
{
|
||||
int n = ARC_TLB_WIRED_ENTRIES;
|
||||
int n = nwired;
|
||||
struct wired_map_entry *entry = wired_map;
|
||||
|
||||
for (; --n >= 0; entry++) {
|
||||
|
|
@ -138,7 +141,7 @@ arc_wired_map_vaddr_entry(va, pap, sizep)
|
|||
paddr_t *pap;
|
||||
vsize_t *sizep;
|
||||
{
|
||||
int n = ARC_TLB_WIRED_ENTRIES;
|
||||
int n = nwired;
|
||||
struct wired_map_entry *entry = wired_map;
|
||||
|
||||
for (; --n >= 0; entry++) {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: cpuregs.h,v 1.33 2000/06/06 17:41:58 soren Exp $ */
|
||||
/* $NetBSD: cpuregs.h,v 1.34 2000/06/09 06:06:59 soda Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1992, 1993
|
||||
|
|
@ -565,7 +565,7 @@
|
|||
|
||||
#define MIPS3_TLB_NUM_TLB_ENTRIES 48
|
||||
#define MIPS_R4300_TLB_NUM_TLB_ENTRIES 32
|
||||
#define MIPS3_TLB_WIRED_ENTRIES 8 /* XXX gross XXX */
|
||||
#define MIPS3_TLB_WIRED_UPAGES 2
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: locore_mips3.S,v 1.33 2000/06/09 04:28:17 soda Exp $ */
|
||||
/* $NetBSD: locore_mips3.S,v 1.34 2000/06/09 06:07:01 soda Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
|
||||
|
|
@ -1096,7 +1096,7 @@ LEAF_NOPROFILE(mips3_TLBInvalidException)
|
|||
dsll k0, k0, 34
|
||||
mfc0 k1, MIPS_COP_0_TLB_INDEX
|
||||
dsrl k0, k0, 34
|
||||
sltiu k1, k1, MIPS3_TLB_WIRED_ENTRIES # Luckily this is MIPS3_PG_G
|
||||
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
|
||||
or k1, k1, k0
|
||||
dmtc0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
|
||||
nop
|
||||
|
|
@ -1125,7 +1125,7 @@ KernTLBIOdd:
|
|||
dsll k0, k0, 34
|
||||
mfc0 k1, MIPS_COP_0_TLB_INDEX
|
||||
dsrl k0, k0, 34
|
||||
sltiu k1, k1, MIPS3_TLB_WIRED_ENTRIES # Luckily this is MIPS3_PG_G
|
||||
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
|
||||
or k1, k1, k0
|
||||
dmtc0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry
|
||||
nop
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: mips_machdep.c,v 1.87 2000/06/08 04:47:13 mhitch Exp $ */
|
||||
/* $NetBSD: mips_machdep.c,v 1.88 2000/06/09 06:07:02 soda Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1998 The NetBSD Foundation, Inc.
|
||||
|
|
@ -52,7 +52,7 @@
|
|||
|
||||
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.87 2000/06/08 04:47:13 mhitch Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.88 2000/06/09 06:07:02 soda Exp $");
|
||||
|
||||
#include "opt_compat_netbsd.h"
|
||||
#include "opt_compat_ultrix.h"
|
||||
|
|
@ -438,7 +438,7 @@ mips_vector_init()
|
|||
case 4:
|
||||
mips3_SetWIRED(0);
|
||||
mips3_TBIA(mips_num_tlb_entries);
|
||||
mips3_SetWIRED(MIPS3_TLB_WIRED_ENTRIES);
|
||||
mips3_SetWIRED(MIPS3_TLB_WIRED_UPAGES);
|
||||
mips3_vector_init();
|
||||
memcpy(mips_locoresw, mips3_locoresw, sizeof(mips_locoresw));
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue