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246 Commits

Author SHA1 Message Date
Stanislav Shwartsman
d18b90484f Added instr callbacks for sysenter/sysexit/syscall/sysret 2008-01-18 08:57:35 +00:00
Stanislav Shwartsman
e287dcd91a correctly implement CLFLUSH protection/paging checks + add instrumentation callback 2008-01-16 22:56:17 +00:00
Stanislav Shwartsman
d9984bb3a1 Eliminate BxResolve call from the heart of cpu loop and move into instructions that really require this calculation. Yes, it blows the code of EVERY CPU method but it has >15% speedup ! 2008-01-10 19:37:56 +00:00
Stanislav Shwartsman
838fb2a048 Fixing V2008 warnings - they found a bug in sse_pfp.cc ! 2007-12-23 17:21:28 +00:00
Stanislav Shwartsman
5d4e32b8da Avoid pointer params for every read_virtual_* except 16-byte SSE and 10-byte x87 reads 2007-12-20 20:58:38 +00:00
Stanislav Shwartsman
b516589e4e Changes in write_virtual_* and pop_* functions -> avoid moving parameteres by pointer 2007-12-20 18:29:42 +00:00
Stanislav Shwartsman
46366b5064 Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions 2007-12-16 21:03:46 +00:00
Stanislav Shwartsman
d9a59c7a1f Added ability to merge traces cross JCC branch instructions 
Makes traces longer -> emulation faster in average
 2007-12-14 20:41:09 +00:00
Stanislav Shwartsman
db69a25c36 Trace cache instrumentation methods 
Next step will be tracing cross non-taken branches
 2007-12-14 11:27:44 +00:00
Stanislav Shwartsman
48d815427c According to AMD docs INVLD/WBINVLD instructions not required to flush TLBs 2007-12-14 10:15:12 +00:00
Stanislav Shwartsman
85d10e4f72 Added MWAIT callback 2007-12-13 21:41:32 +00:00
Stanislav Shwartsman
91e0db63c4 no need to invalidate prefetch queue for RDMSR/WRMSR 2007-12-03 21:43:14 +00:00
Stanislav Shwartsman
c58e95f611 Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well 2007-12-03 20:49:24 +00:00
Stanislav Shwartsman
8cfd17202a some simple SSE code optimizations 2007-11-27 22:12:45 +00:00
Stanislav Shwartsman
48650a70b4 Optimized alignment check 2007-11-20 21:22:03 +00:00
Stanislav Shwartsman
e1496bb9e0 Small optimization 2007-11-18 18:40:38 +00:00
Stanislav Shwartsman
d9e58bd598 split11b on opcode tables level - split almost eevery splittable instruction 
will be continued
 2007-11-17 12:44:10 +00:00
Stanislav Shwartsman
24e1936fbb Fixed compilation warning when compiling with no x86-64 2007-11-09 12:06:34 +00:00
Stanislav Shwartsman
5a172541e2 Small cleanup 2007-11-01 20:43:53 +00:00
Stanislav Shwartsman
e137560b14 Complete MONITOR/MWAIT implemntation (including monitoring of memory range) 
Fixed PANIC in read/write Cr/Dr - should #UD with unkown register used
 2007-11-01 18:03:48 +00:00
Stanislav Shwartsman
4ec7f5df39 Optimize access to IP (16 bit) - made IP register similar to GPR 2007-10-18 22:44:39 +00:00
Stanislav Shwartsman
082eb05b6b First step to fully configurable CPUID 
- put CPUID functions data into array, in future we could load this array from configure file
 - cpuid initialize function is more flexible now but still reuire some work
 2007-10-12 19:30:51 +00:00
Stanislav Shwartsman
8adbbcf17c Started first implementation of MONITOR/MWAIT 2007-10-11 21:29:01 +00:00
Stanislav Shwartsman
f6ed95785f added cpu state param - for future use and for dbg info 
started to move debugger to info bx_param interface -> info sse and info mmx commands modified
 2007-10-11 18:12:00 +00:00
Stanislav Shwartsman
82b7eaabd5 CLFLUSH do not fault when checking execute only segment 2007-10-10 21:48:46 +00:00
Stanislav Shwartsman
071c5c1a26 A lot of changes but everything is really trivial. 
Make save/restore default feature, the configure option for save/restore removed from configure script and save/restore made available forever. All code now assume it is exists. Bochs save/restore tree previosly called "save_restore" renamed to "bochs" tree and it will be havily used everywhere, starting from save/restore and ending by various bochs debugger functions. I am going to rework debugger code to get rid of debug CPU access functions and use this "bochs" param tree instead
 2007-09-28 19:52:08 +00:00
Stanislav Shwartsman
e812f81e7b Fixes in zero upper ECX 2007-09-25 16:11:32 +00:00
Stanislav Shwartsman
91e6ca8d5c Implemented MTRR support 
Fixes in #PF exception priority
 2007-09-20 17:33:35 +00:00
Stanislav Shwartsman
70f513b07b Make efer control MSR separate register 2007-09-10 20:47:08 +00:00
Stanislav Shwartsman
895891b673 Implemented #AC check under configure option 
Fixes in misaligned SSE support
 2007-07-31 20:25:52 +00:00
Stanislav Shwartsman
38d1f39c77 Converted CR0 bits to one register similar to CR4 - a bit slower but helps with other features implemntation 2007-07-09 15:16:14 +00:00
Stanislav Shwartsman
7c6c2bb520 Removed PANIC message 2007-06-08 09:25:30 +00:00
Stanislav Shwartsman
65a99eb736 Change BX_ERROR to BX_DEBUG 2007-04-25 20:14:15 +00:00
Stanislav Shwartsman
6c139a9c8c Define LIN and PHY address size in config.h 2007-04-14 10:05:30 +00:00
Stanislav Shwartsman
d3252fbc1c Removed unneeded invalidate_prefetch_q from RDMSR instruction 2007-02-23 22:08:43 +00:00
Stanislav Shwartsman
c24627c00f Implemented CLFLUSH instruction 
Set of minor fixes for correctness
 2007-01-28 21:27:31 +00:00
Stanislav Shwartsman
6c63e84d23 Fixed CR3 masking in long mode 
Added PANIC assertion of 32-bit physical address in PAE mode
cleanup
 2006-10-04 19:08:40 +00:00
Stanislav Shwartsman
02c2fc9e89 Fixed priveledge level checks 2006-09-10 16:56:55 +00:00
Stanislav Shwartsman
fdac9efa9b Fixed ton of code duplication. 
Do not save/restore XMM8-XMM15 not in 64-bit mode
 2006-08-31 18:18:17 +00:00
Stanislav Shwartsman
65082e4a4f Handle granularity field for LDT 
Next step - fix code duplication with TSS
 2006-08-25 19:56:03 +00:00
Stanislav Shwartsman
3ce7764fce Fixes in 64-bit decoding 2006-08-11 17:23:36 +00:00
Stanislav Shwartsman
45353d5e6f Fixed DR registers handling in x86-64 mode 2006-06-26 21:07:44 +00:00
Stanislav Shwartsman
9269288319 Fix SR macros mis-use. Need to add assertion into bxlist_c and check that it has no 2 params with same name inside ! 2006-06-14 16:44:33 +00:00
Stanislav Shwartsman
49d7b4614f Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits 2006-06-12 16:58:27 +00:00
Stanislav Shwartsman
308521e7ce Fixes in SYSCALL/SYSRET instructions 
Use parse_selector to avoid code duplication
 2006-06-11 21:37:22 +00:00
Stanislav Shwartsman
6c3420a18b Add debug prints before any #GP excepion which only possible to be generated 2006-06-09 22:29:07 +00:00
Stanislav Shwartsman
8b55085c76 Merge tss286 and tss386 segment descriptor cache fields to one structure 2006-05-21 20:41:48 +00:00
Stanislav Shwartsman
f4c7b4074e Support for x86-64 in x86 debugger (DR0-DR7) 2006-05-13 12:49:45 +00:00
Stanislav Shwartsman
9a32d0e98f Optimize debug registers handling 2006-05-13 12:29:12 +00:00
Stanislav Shwartsman
63dc4d4e10 Fixed CR4 GP(0) condition (patch by no_mayl in mailing list) 2006-04-23 16:11:16 +00:00
Stanislav Shwartsman
d972e4a4b7 Fixed CR3 restore in RSM instruction 
Added HALT state indication (actually make existant one working for single CPU)
 2006-04-10 19:05:21 +00:00
Stanislav Shwartsman
45f30f0a4c some code written to enter CPU to shutdown state. 
finally the shutdown handling should be done exactly as in VmWare - the GUI should ask user if the CPU should reset and go to HLT/IF=0 if user choosed to stay in shutdown mode.
CPU configure option reset-on-triple-failt should be extended to shutdown-reset=0|1
small code cleanups and fixes
 2006-04-07 20:47:32 +00:00
Stanislav Shwartsman
f8c3968d42 Changes list made after CVS service crash: 
- Fixed critical bug in CPU code added with one of the prev commits
  - Disasm support for SSE4
  - Rename PNI->SSE3 everywhere in the code
  - Correctly decode, disassemble and execute 'XCHG R8, rAX' x86-64 instruction
  - Correctly decode, disassemble and execute multi-byte NOP 0F F1 opcode
  - Fixed ENTER and LEAVE instructions in x86-64 mode
  - Added ability to turn ON instruction trace, only GUI support is missed.
    Instruction trace could be enabled if Bochs was compiled with disasm
  - More changes Bit32u -> bx_phy_address
  - Complete preliminary implementation of SMM in Bochs, SMI is still PANICs but if you press 'continue' everything should work OK
  - Small code cleanup
  - Update CHANGES and user docs
 2006-04-05 17:31:35 +00:00
Stanislav Shwartsman
da3d26d7f4 Preliminary implemntation of SMM save statei 
Fixed fetchModeMask for load32bitOsStack
 2006-03-27 18:02:07 +00:00
Stanislav Shwartsman
f347ab97bf Fixed CALL/JMP far through call gate 64 
Decode SWAPGS and RDTSCP instructions
Indent changes in fetchdecode
 2006-03-22 20:47:11 +00:00
Stanislav Shwartsman
a64b16391d Remove unused vars 2006-03-15 17:57:11 +00:00
Stanislav Shwartsman
e85a90a720 Remove cpu.h -> devices.cc dependancy, kill_bochs_request moved from CPU to bx_pc_system 
Small Icache simplification and speedup
 2006-03-14 18:11:22 +00:00
Stanislav Shwartsman
7b6c2587a9 Now devices could be compiled separatelly from CPU 
Averything that required cpu.h include now has it explicitly and there are a lot of files not dependant by CPU at all which will compile a lot faster now ...
 2006-03-06 22:03:16 +00:00
Stanislav Shwartsman
324d75e749 Fix another broking change 2006-03-04 09:22:55 +00:00
Stanislav Shwartsman
5fad793989 move local apic handling to the access_linear function for the memory class. 
speedup the whole simulation by 2% !
 2006-03-01 22:32:24 +00:00
Stanislav Shwartsman
a527b2cfca first smm - implement cpu state when switching to SMM 
smm coming soon
fixed code duplication in init.cc
 2006-02-28 19:50:08 +00:00
Stanislav Shwartsman
55ceecf79b Small optimization in icache page-write-stamp 2006-02-28 17:47:33 +00:00
Stanislav Shwartsman
024ce249bf Define SMM mode for future implementation. 
I would like all next commits be aware of SMM mode.
It can't be implemented right now (too many questions w/o answers) but it will be done till next major release definitelly.
 2006-02-14 19:00:08 +00:00
Stanislav Shwartsman
9b451f43e2 Save/restore RIP/RSP only on FAULT type exceptions, not on traps 2006-02-11 09:08:02 +00:00
Stanislav Shwartsman
9a15f59e05 Fixed bug in SYSRET legacy mode 2006-02-02 17:55:48 +00:00
Stanislav Shwartsman
9df8079206 Write to MSR_TSC implemented (patch by Bryce) 2006-01-21 12:06:03 +00:00
Stanislav Shwartsman
7bf51e48db Print FS_MSR_BASE and GS_MSR_BASE to debug registers dump (requested in bug report [ 1406387 ] JMP instruction should display absolute address) 
Fixed fetch mode mask initialization (bug report 1400027  Boundary instruction cache error for uninitialized memory)
For safety only - everytime when changing CS register update fetch mode mask.
Actually it need to be updated everytime when there is a chance for execute mode change or 16/32 bit mode change.
 2006-01-16 19:22:28 +00:00
Stanislav Shwartsman
a74b63eb3d Allow writing PCE to CR4 2006-01-13 11:11:29 +00:00
Stanislav Shwartsman
393a653fb4 Fix typo 2006-01-05 21:40:07 +00:00
Stanislav Shwartsman
70cc5a7fb0 Fix incorrect commit 2005-12-12 19:54:48 +00:00
Stanislav Shwartsman
f863d1e902 Generate #GP exception instead of #TS when TSS selector points to bad TSS 2005-12-12 19:44:06 +00:00
Stanislav Shwartsman
fe02ecab65 Do not flood log with WBINVD/INVD messages 2005-11-27 18:36:19 +00:00
Stanislav Shwartsman
8c91790680 Redefine registers accessors in cpu.h 
Change BxSupportPAE and BxSupportGlobalPages macros to Bochs style names
Set bx_cpu_id in BX_CPU_C constructor (safe way)
Backup cpu-level check for paging features at compile time (already checked in configure)
Some warnings and indent fixes
speed up get_segment_base method for x86-64 case
 2005-11-26 21:36:51 +00:00
Stanislav Shwartsman
9314752bb1 Rewritten task_switch mechnism according to AMD docs 
This should fix the #SF bug report
736279  Jump to Task
 2005-11-21 21:10:59 +00:00
Stanislav Shwartsman
cd2a9f317d Do not PANIC when HLT with IF=0, only BX_INFO 2005-11-04 15:15:02 +00:00
Stanislav Shwartsman
ab81296e33 Update CHANGES/TODO 
Change BX_INFO to BX_DEBUG in read CR4 function
 2005-10-23 21:11:32 +00:00
Stanislav Shwartsman
64ba97210b INVD/WBINVD should flush caches and TLB 2005-10-18 18:07:52 +00:00
Stanislav Shwartsman
670395f1be VME support - beta #1 2005-10-17 13:06:09 +00:00
Stanislav Shwartsman
e83c77db49 Preparing to VME implementation 
DO NOT ENABLE VME option until the implementation will be completed !
 2005-10-16 23:13:19 +00:00
Stanislav Shwartsman
469358aaf9 Move SHOW_IPS action to bx_gui object, may be some GUI will be able to print IPS online in the simulation window status bar ... 
Small code cleanup
 2005-10-13 16:22:21 +00:00
Stanislav Shwartsman
39fc11c5da Fix compilation error 2005-10-09 18:32:36 +00:00
Stanislav Shwartsman
7869ab425f LTR should #GP when loading NULL selector 
fixed check for SYSENTER/SYSEXIT instructions
according to new Intel references
 2005-10-01 07:47:00 +00:00
Stanislav Shwartsman
8c783bc329 Fixed cpu_mode corruption in x86-64 mode 
Removed all potentially unsafe and duplicated code in setFLAGS methods to avoid such kind of problems in future
 2005-09-29 17:32:32 +00:00
Stanislav Shwartsman
6096698393 Fixed CLTS and HLT GP0 check 2005-09-14 20:01:42 +00:00
Stanislav Shwartsman
8be190d848 Implemented RDTSCP instruction 2005-08-05 12:47:33 +00:00
Stanislav Shwartsman
954aae3f99 Speedup push/pop operations, they actually not needed to do can_push/can_pop checkes, the same checkes already done in read/write_virtial methods 
Split push_seg_reg methods according to op size
 2005-07-31 17:57:27 +00:00
Stanislav Shwartsman
5da36b7d3d Fixed code duplication, added canonical address checking for RETF in long mode 2005-07-29 06:29:57 +00:00
Stanislav Shwartsman
4638f09b24 Added BX_INSTR_HLT instrumentation callback 2005-07-07 18:40:35 +00:00
Stanislav Shwartsman
3d2e2162f3 Code indent, no functionality changes 2005-07-01 14:06:02 +00:00
Stanislav Shwartsman
015ad92958 Added SMP status to TODO file 
Removed abusive BX_INFO from WBINVD instruction
The PREFETCHW (3DNow!) instruction should not #UD in x86-64 even on Intel w/o 3DNow!
 2005-05-27 01:53:38 +00:00
Stanislav Shwartsman
6c318bd047 SFENCE/MFENCE/LFENCE methods not defined in CPU class and they NOP in fetchdecode.cc 2005-05-18 05:05:40 +00:00
Kevin Lawton
f829c9cf93 Typo in CR8 handling in MOV_CqRq/MOV_RqCq had a typo. A switch 
target of 7 was used instead of 8.
 2005-05-17 22:22:35 +00:00
Stanislav Shwartsman
494af8b1f3 Fixed segmentation fault for 2CPU cfg 2005-04-26 19:19:58 +00:00
Stanislav Shwartsman
501cca67c2 Fix compilation err 2005-04-18 17:41:15 +00:00
Stanislav Shwartsman
8482511af3 Fix compilation errors 
Add BX_INFO for writing to TSC_MSR (not implemented message)
 2005-04-18 17:21:34 +00:00
Stanislav Shwartsman
0f7f728e86 Added debug messages for interrupt function in long mode 
Added mode switch debug prints
 2005-03-30 20:53:04 +00:00
Stanislav Shwartsman
e6e9dd3825 Extend Bochs instrumentation 
Compatability fixes
 2005-03-17 20:50:57 +00:00
Stanislav Shwartsman
6e53a54907 Extend cpu_mode for : 
#define BX_MODE_IA32_REAL       0x0   // CR0.PE=0
#define BX_MODE_IA32_PROTECTED  0x1   // CR0.PE=1, EFLAGS.VM=0
#define BX_MODE_IA32_V8086      0x2   // CR0.PE=1, EFLAGS.VM=1
#define BX_MODE_LONG_COMPAT     0x3   // EFER.LMA = 0, EFER.LME = 1
#define BX_MODE_LONG_64         0x4   // EFER.LMA = 1, EFER.LME = 1
 2005-03-15 19:00:04 +00:00
Stanislav Shwartsman
c30e89289b Fixed R/O pages access in CPL=3 (TLB accessBits bug) 2005-03-03 20:24:52 +00:00
Stanislav Shwartsman
c583a6f9cf move segments and descriptors definitions and macroses for new descriptor.h 2005-02-27 17:41:45 +00:00