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Fixed another bug generator - duplication between descriptor type field and four descriptor cache bits

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This commit is contained in:
Stanislav Shwartsman 2006-06-12 16:58:27 +00:00
parent 5a80bf51ca
commit 49d7b4614f
19 changed files with 356 additions and 481 deletions
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15
bochs/bx_debug/dbg_main.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dbg_main.cc,v 1.69 2006-06-11 16:40:37 sshwarts Exp $
// $Id: dbg_main.cc,v 1.70 2006-06-12 16:58:26 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -3434,11 +3434,16 @@ Bit32u bx_dbg_get_laddr(Bit16u sel, Bit32u ofs)
}
Bit32u lowaddr, highaddr;
if (descriptor.u.segment.c_ed && !descriptor.u.segment.executable) // expand-down
lowaddr = descriptor.u.segment.limit_scaled,
// expand-down
if (IS_DATA_SEGMENT(descriptor.type) && IS_DATA_SEGMENT_EXPAND_DOWN(descriptor.type)) {
lowaddr = descriptor.u.segment.limit_scaled;
highaddr = descriptor.u.segment.g ? 0xffffffff : 0xffff;
else
lowaddr = 0, highaddr = descriptor.u.segment.limit_scaled;
}
else {
lowaddr = 0;
highaddr = descriptor.u.segment.limit_scaled;
}
if ((ofs < lowaddr) || (ofs > highaddr)) {
dbg_printf("WARNING: Offset %08X is out of selector %04x limit (%08x...%08x)!\n",

4
bochs/bx_debug/lexer.c
View File

@ -19,7 +19,7 @@
/* A lexical scanner generated by flex */
/* Scanner skeleton version:
* $Header: /home/volker/Archiv/bochs-cvs-rsync-20110222/bochs/bx_debug/lexer.c,v 1.20 2006-06-11 18:03:44 sshwarts Exp $
* $Header: /home/volker/Archiv/bochs-cvs-rsync-20110222/bochs/bx_debug/lexer.c,v 1.21 2006-06-12 16:58:26 sshwarts Exp $
*/
#define FLEX_SCANNER
@ -1055,7 +1055,7 @@ char *yytext;
#define INITIAL 0
#line 2 "lexer.l"
/////////////////////////////////////////////////////////////////////////
// $Id: lexer.c,v 1.20 2006-06-11 18:03:44 sshwarts Exp $
// $Id: lexer.c,v 1.21 2006-06-12 16:58:26 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
#include <stdlib.h>

20
bochs/cpu/call_far.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: call_far.cc,v 1.11 2006-06-09 22:29:06 sshwarts Exp $
// $Id: call_far.cc,v 1.12 2006-06-12 16:58:26 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -234,7 +234,7 @@ BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address disp)
// DPL of selected descriptor must be <= CPL,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("call_protected: selected descriptor is not code"));
@ -249,8 +249,7 @@ BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address disp)
// CALL GATE TO MORE PRIVILEGE
// if non-conforming code segment and DPL < CPL then
if ( (cs_descriptor.u.segment.c_ed==0) &&
(cs_descriptor.dpl < CPL) )
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit16u SS_for_cpl_x;
Bit32u ESP_for_cpl_x;
@ -298,11 +297,11 @@ BX_CPU_C::call_protected(bxInstruction_c *i, Bit16u cs_raw, bx_address disp)
// descriptor must indicate writable data segment,
// else #TS(SS selector)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable ||
ss_descriptor.u.segment.r_w==0)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("call_protected: ss descriptor not writable data seg"));
BX_ERROR(("call_protected: ss descriptor is not writable data seg"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
@ -494,7 +493,7 @@ BX_CPU_C::call_gate64(bx_selector_t *gate_selector)
// DPL of selected descriptor must be <= CPL,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl > CPL)
{
BX_ERROR(("call_gate64: selected descriptor is not code"));
@ -520,8 +519,7 @@ BX_CPU_C::call_gate64(bx_selector_t *gate_selector)
// CALL GATE TO MORE PRIVILEGE
// if non-conforming code segment and DPL < CPL then
if ( (cs_descriptor.u.segment.c_ed==0) &&
(cs_descriptor.dpl < CPL) )
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit64u RSP_for_cpl_x;

8
bochs/cpu/ctrl_xfer_pro.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: ctrl_xfer_pro.cc,v 1.54 2006-05-12 17:04:19 sshwarts Exp $
// $Id: ctrl_xfer_pro.cc,v 1.55 2006-06-12 16:58:26 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -41,8 +41,8 @@
void BX_CPU_C::check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_rpl, Bit8u check_cpl)
{
// descriptor AR byte must indicate code segment else #GP(selector)
if ((descriptor->valid==0) || (descriptor->segment==0) ||
(descriptor->u.segment.executable==0))
if (descriptor->valid==0 || descriptor->segment==0 ||
IS_DATA_SEGMENT(descriptor->type))
{
BX_ERROR(("check_cs: not a valid code segment !"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);
@ -63,7 +63,7 @@ void BX_CPU_C::check_cs(bx_descriptor_t *descriptor, Bit16u cs_raw, Bit8u check_
#endif
// if non-conforming, code segment descriptor DPL must = CPL else #GP(selector)
if (descriptor->u.segment.c_ed==0) {
if (IS_CODE_SEGMENT_NON_CONFORMING(descriptor->type)) {
if (descriptor->dpl != check_cpl) {
BX_ERROR(("check_cs: non-conforming code seg descriptor dpl != cpl"));
exception(BX_GP_EXCEPTION, cs_raw & 0xfffc, 0);

67
bochs/cpu/debugstuff.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: debugstuff.cc,v 1.70 2006-06-11 16:40:37 sshwarts Exp $
// $Id: debugstuff.cc,v 1.71 2006-06-12 16:58:26 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -346,15 +346,10 @@ bx_bool BX_CPU_C::dbg_set_reg(unsigned reg, Bit32u val)
seg->cache.p = 1;
seg->cache.dpl = 0;
seg->cache.segment = 1; // regular segment
if (reg == BX_DBG_REG_CS) {
seg->cache.u.segment.executable = 1; // code segment
}
else {
seg->cache.u.segment.executable = 0; // data segment
}
seg->cache.u.segment.c_ed = 0; // expand up/non-conforming
seg->cache.u.segment.r_w = 1; // writeable
seg->cache.u.segment.a = 1; // accessed
if (reg == BX_DBG_REG_CS)
seg->cache.type = BX_CODE_EXEC_READ_ACCESSED;
else
seg->cache.type = BX_DATA_READ_WRITE_ACCESSED;
seg->cache.u.segment.base = val << 4;
seg->cache.u.segment.limit = 0xffff;
seg->cache.u.segment.limit_scaled = 0xffff;
@ -614,10 +609,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = (cpu->cs.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = (cpu->cs.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = (cpu->cs.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = (cpu->cs.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = (cpu->cs.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = (cpu->cs.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = (cpu->cs.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = (cpu->cs.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base |= (cpu->cs.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base |= (cpu->cs.des_h & 0xff000000);
@ -648,10 +639,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = (cpu->ss.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = (cpu->ss.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = (cpu->ss.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = (cpu->ss.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = (cpu->ss.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = (cpu->ss.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = (cpu->ss.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = (cpu->ss.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base |= (cpu->ss.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base |= (cpu->ss.des_h & 0xff000000);
@ -678,10 +665,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = (cpu->ds.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = (cpu->ds.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = (cpu->ds.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = (cpu->ds.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = (cpu->ds.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = (cpu->ds.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = (cpu->ds.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base = (cpu->ds.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base |= (cpu->ds.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base |= (cpu->ds.des_h & 0xff000000);
@ -708,10 +691,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = (cpu->es.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = (cpu->es.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.type = (cpu->es.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.executable = (cpu->es.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = (cpu->es.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.r_w = (cpu->es.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.a = (cpu->es.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base = (cpu->es.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base |= (cpu->es.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base |= (cpu->es.des_h & 0xff000000);
@ -738,10 +717,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.dpl = (cpu->fs.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.segment = (cpu->fs.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.type = (cpu->fs.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.executable = (cpu->fs.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.c_ed = (cpu->fs.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.r_w = (cpu->fs.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.a = (cpu->fs.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base = (cpu->fs.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base |= (cpu->fs.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base |= (cpu->fs.des_h & 0xff000000);
@ -768,10 +743,6 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.dpl = (cpu->gs.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.segment = (cpu->gs.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.type = (cpu->gs.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.executable = (cpu->gs.des_h >> 11) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.c_ed = (cpu->gs.des_h >> 10) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.r_w = (cpu->gs.des_h >> 9) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.a = (cpu->gs.des_h >> 8) & 0x01;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base = (cpu->gs.des_l >> 16);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base |= (cpu->gs.des_h & 0xff) << 16;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base |= (cpu->gs.des_h & 0xff000000);
@ -793,15 +764,15 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR ldtr.selector.ti = (cpu->ldtr.sel >> 2) & 0x01;
BX_CPU_THIS_PTR ldtr.selector.rpl = cpu->ldtr.sel & 0x03;
BX_CPU_THIS_PTR ldtr.cache.valid = cpu->ldtr.valid;
BX_CPU_THIS_PTR ldtr.cache.p = (cpu->ldtr.des_h >> 15) & 0x01;
BX_CPU_THIS_PTR ldtr.cache.dpl = (cpu->ldtr.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR ldtr.cache.segment = (cpu->ldtr.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR ldtr.cache.type = (cpu->ldtr.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base = (cpu->ldtr.des_l >> 16);
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff) << 16;
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff000000);
BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit = (cpu->ldtr.des_l & 0xffff);
BX_CPU_THIS_PTR ldtr.cache.valid = cpu->ldtr.valid;
BX_CPU_THIS_PTR ldtr.cache.p = (cpu->ldtr.des_h >> 15) & 0x01;
BX_CPU_THIS_PTR ldtr.cache.dpl = (cpu->ldtr.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR ldtr.cache.segment = (cpu->ldtr.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR ldtr.cache.type = (cpu->ldtr.des_h >> 8) & 0x0f;
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base = (cpu->ldtr.des_l >> 16);
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff) << 16;
BX_CPU_THIS_PTR ldtr.cache.u.ldt.base |= (cpu->ldtr.des_h & 0xff000000);
BX_CPU_THIS_PTR ldtr.cache.u.ldt.limit = (cpu->ldtr.des_l & 0xffff);
// TR
type = (cpu->tr.des_h >> 8) & 0x0f;
@ -811,11 +782,11 @@ bx_bool BX_CPU_C::dbg_set_cpu(bx_dbg_cpu_t *cpu)
BX_CPU_THIS_PTR tr.selector.ti = (cpu->tr.sel >> 2) & 0x01;
BX_CPU_THIS_PTR tr.selector.rpl = cpu->tr.sel & 0x03;
BX_CPU_THIS_PTR tr.cache.valid = cpu->tr.valid;
BX_CPU_THIS_PTR tr.cache.p = (cpu->tr.des_h >> 15) & 0x01;
BX_CPU_THIS_PTR tr.cache.dpl = (cpu->tr.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR tr.cache.segment = (cpu->tr.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR tr.cache.type = type;
BX_CPU_THIS_PTR tr.cache.valid = cpu->tr.valid;
BX_CPU_THIS_PTR tr.cache.p = (cpu->tr.des_h >> 15) & 0x01;
BX_CPU_THIS_PTR tr.cache.dpl = (cpu->tr.des_h >> 13) & 0x03;
BX_CPU_THIS_PTR tr.cache.segment = (cpu->tr.des_h >> 12) & 0x01;
BX_CPU_THIS_PTR tr.cache.type = type;
if (type == BX_SYS_SEGMENT_AVAIL_286_TSS) {
BX_CPU_THIS_PTR tr.cache.u.tss.base = (cpu->tr.des_l >> 16);
BX_CPU_THIS_PTR tr.cache.u.tss.base |= (cpu->tr.des_h & 0xff) << 16;

29
bochs/cpu/descriptor.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: descriptor.h,v 1.13 2006-06-11 21:55:39 sshwarts Exp $
// $Id: descriptor.h,v 1.14 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -113,11 +113,6 @@ typedef struct
union {
struct {
bx_bool executable; /* 1=code, 0=data or stack segment */
bx_bool c_ed; /* for code: 1=conforming,
for data/stack: 1=expand down */
bx_bool r_w; /* for code: readable?, for data/stack: writeable? */
bx_bool a; /* accessed? */
bx_address base; /* base address: 286=24bits, 386=32bits, long=64 */
Bit32u limit; /* limit: 286=16bits, 386=20bits */
Bit32u limit_scaled; /* for efficiency, this contrived field is set to
@ -170,11 +165,29 @@ union {
#define IS_PRESENT(descriptor) (descriptor.p)
#if BX_SUPPORT_X86_64
#define IS_LONG64_SEGMENT(descriptor) (descriptor.u.segment.l)
#define IS_LONG64_SEGMENT(descriptor) (descriptor.u.segment.l)
#else
#define IS_LONG64_SEGMENT(descriptor) (0)
#define IS_LONG64_SEGMENT(descriptor) (0)
#endif
#define IS_CODE_SEGMENT(type) (((type) >> 3) & 0x1)
#define IS_CODE_SEGMENT_CONFORMING(type) (((type) >> 2) & 0x1)
#define IS_DATA_SEGMENT_EXPAND_DOWN(type) (((type) >> 2) & 0x1)
#define IS_CODE_SEGMENT_READABLE(type) (((type) >> 1) & 0x1)
#define IS_DATA_SEGMENT_WRITEABLE(type) (((type) >> 1) & 0x1)
#define IS_SEGMENT_ACCESSED(type) ( (type) & 0x1)
#define BX_SEGMENT_CODE (0x8)
#define BX_SEGMENT_DATA_EXPAND_DOWN (0x4)
#define BX_SEGMENT_CODE_CONFORMING (0x4)
#define BX_SEGMENT_DATA_WRITE (0x2)
#define BX_SEGMENT_CODE_READ (0x2)
#define BX_SEGMENT_ACCESSED (0x1)
#define IS_DATA_SEGMENT(type) (! IS_CODE_SEGMENT(type))
#define IS_CODE_SEGMENT_NON_CONFORMING(type) \
(! IS_CODE_SEGMENT_CONFORMING(type))
typedef struct {
bx_selector_t selector;
bx_descriptor_t cache;

132
bochs/cpu/exception.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: exception.cc,v 1.79 2006-06-09 22:29:06 sshwarts Exp $
// $Id: exception.cc,v 1.80 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -127,7 +127,7 @@ void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
// examine CS selector and descriptor given in gate descriptor
// selector must be non-null else #GP(EXT)
if ( (gate_dest_selector & 0xfffc) == 0 ) {
if ((gate_dest_selector & 0xfffc) == 0) {
BX_ERROR(("int_trap_gate(long mode): selector null"));
exception(BX_GP_EXCEPTION, 0, 0);
}
@ -141,9 +141,8 @@ void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
// descriptor AR byte must indicate code seg
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
if ( cs_descriptor.valid==0 ||
cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0 ||
if ( cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl>CPL)
{
BX_ERROR(("interrupt(long mode): not code segment"));
@ -165,7 +164,8 @@ void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
// if code segment is non-conforming and DPL < CPL then
// INTERRUPT TO INNER PRIVILEGE:
if ((cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL) || (ist > 0))
if ((IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type)
&& cs_descriptor.dpl<CPL) || (ist > 0))
{
Bit64u RSP_for_cpl_x;
@ -217,22 +217,22 @@ void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
// push long pointer to return address onto new stack
push_64(old_CS);
push_64(old_RIP);
if ( is_error_code )
if (is_error_code)
push_64(error_code);
// if INTERRUPT GATE set IF to 0
if ( !(gate_descriptor.type & 1) ) // even is int-gate
BX_CPU_THIS_PTR clear_IF ();
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_VM ();
BX_CPU_THIS_PTR clear_RF ();
BX_CPU_THIS_PTR clear_NT ();
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_VM();
BX_CPU_THIS_PTR clear_RF();
BX_CPU_THIS_PTR clear_NT();
return;
}
// if code segment is conforming OR code segment DPL = CPL then
// INTERRUPT TO SAME PRIVILEGE LEVEL:
if (cs_descriptor.u.segment.c_ed || cs_descriptor.dpl==CPL)
if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
{
BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE"));
@ -255,28 +255,26 @@ void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
push_64(read_eflags());
push_64(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_64(RIP);
if ( is_error_code )
if (is_error_code)
push_64(error_code);
// set the RPL field of CS to CPL
branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL);
// if interrupt gate then set IF to 0
if ( !(gate_descriptor.type & 1) ) // even is int-gate
BX_CPU_THIS_PTR clear_IF ();
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_VM ();
BX_CPU_THIS_PTR clear_RF ();
BX_CPU_THIS_PTR clear_NT ();
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_VM();
BX_CPU_THIS_PTR clear_RF();
BX_CPU_THIS_PTR clear_NT();
return;
}
// else #GP(CS selector + ext)
BX_ERROR(("interrupt(long mode): bad descriptor"));
BX_ERROR(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
(unsigned) cs_descriptor.u.segment.c_ed,
(unsigned) cs_descriptor.dpl,
(unsigned) CPL));
BX_ERROR(("type=%u, descriptor.dpl=%u, CPL=%u",
(unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL));
BX_ERROR(("cs.segment = %u", (unsigned) cs_descriptor.segment));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
}
@ -389,7 +387,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// stack limits must allow push of 2 more bytes, else #SS(0)
// push error code onto stack
if ( is_error_code ) {
if (is_error_code) {
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b)
push_32(error_code);
else
@ -408,7 +406,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
case BX_286_TRAP_GATE:
case BX_386_INTERRUPT_GATE:
case BX_386_TRAP_GATE:
if ( gate_descriptor.type >= 14 ) { // 386 gate
if (gate_descriptor.type >= 14) { // 386 gate
gate_dest_selector = gate_descriptor.u.gate386.dest_selector;
gate_dest_offset = gate_descriptor.u.gate386.dest_offset;
}
@ -419,7 +417,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// examine CS selector and descriptor given in gate descriptor
// selector must be non-null else #GP(EXT)
if ( (gate_dest_selector & 0xfffc) == 0 ) {
if ((gate_dest_selector & 0xfffc) == 0) {
BX_ERROR(("int_trap_gate(): selector null"));
exception(BX_GP_EXCEPTION, 0, 0);
}
@ -433,10 +431,9 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// descriptor AR byte must indicate code seg
// and code segment descriptor DPL<=CPL, else #GP(selector+EXT)
if ( cs_descriptor.valid==0 ||
cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0 ||
cs_descriptor.dpl>CPL )
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
IS_DATA_SEGMENT(cs_descriptor.type) ||
cs_descriptor.dpl>CPL)
{
BX_ERROR(("interrupt(): not code segment"));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
@ -450,7 +447,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// if code segment is non-conforming and DPL < CPL then
// INTERRUPT TO INNER PRIVILEGE:
if (cs_descriptor.u.segment.c_ed==0 && cs_descriptor.dpl<CPL)
if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && (cs_descriptor.dpl < CPL))
{
Bit16u old_SS, old_CS, SS_for_cpl_x;
Bit32u ESP_for_cpl_x, old_EIP, old_ESP;
@ -472,8 +469,8 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
&SS_for_cpl_x, &ESP_for_cpl_x);
// Selector must be non-null else #TS(EXT)
if ( (SS_for_cpl_x & 0xfffc) == 0 ) {
BX_PANIC(("interrupt(): SS selector null"));
if ((SS_for_cpl_x & 0xfffc) == 0) {
BX_ERROR(("interrupt(): SS selector null"));
exception(BX_TS_EXCEPTION, 0, 0); /* TS(ext) */
}
@ -487,25 +484,24 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// selector rpl must = dpl of code segment,
// else #TS(SS selector + ext)
if (ss_selector.rpl != cs_descriptor.dpl) {
BX_PANIC(("interrupt(): SS.rpl != CS.dpl"));
BX_ERROR(("interrupt(): SS.rpl != CS.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// stack seg DPL must = DPL of code segment,
// else #TS(SS selector + ext)
if (ss_descriptor.dpl != cs_descriptor.dpl) {
BX_PANIC(("interrupt(): SS.dpl != CS.dpl"));
BX_ERROR(("interrupt(): SS.dpl != CS.dpl"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
// descriptor must indicate writable data segment,
// else #TS(SS selector + EXT)
if (ss_descriptor.valid==0 ||
ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable==1 ||
ss_descriptor.u.segment.r_w==0)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_PANIC(("interrupt(): SS not writable data segment"));
BX_ERROR(("interrupt(): SS is not writable data segment"));
exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
}
@ -538,7 +534,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
}
// new stack must have enough room, else #SS(seg selector)
if ( !can_push(&ss_descriptor, ESP_for_cpl_x, bytes) )
if (!can_push(&ss_descriptor, ESP_for_cpl_x, bytes))
{
BX_DEBUG(("interrupt(): new stack doesn't have room for %u bytes", (unsigned) bytes));
exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc, 0);
@ -572,12 +568,12 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
Bit32u eflags = read_eflags();
// if INTERRUPT GATE set IF to 0
if ( !(gate_descriptor.type & 1) ) // even is int-gate
BX_CPU_THIS_PTR clear_IF ();
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_VM ();
BX_CPU_THIS_PTR clear_RF ();
BX_CPU_THIS_PTR clear_NT ();
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_VM();
BX_CPU_THIS_PTR clear_RF();
BX_CPU_THIS_PTR clear_NT();
if (is_v8086_mode)
{
@ -646,7 +642,7 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
// if code segment is conforming OR code segment DPL = CPL then
// INTERRUPT TO SAME PRIVILEGE LEVEL:
if ( cs_descriptor.u.segment.c_ed==1 || cs_descriptor.dpl==CPL )
if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL)
{
int bytes;
Bit32u temp_ESP;
@ -691,14 +687,14 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
push_32(read_eflags());
push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_32(EIP);
if ( is_error_code )
if (is_error_code)
push_32(error_code);
}
else { // 286 gate
push_16(read_flags());
push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value);
push_16(IP);
if ( is_error_code )
if (is_error_code)
push_16(error_code);
}
@ -709,20 +705,19 @@ void BX_CPU_C::protected_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error
EIP = gate_dest_offset;
// if interrupt gate then set IF to 0
if ( !(gate_descriptor.type & 1) ) // even is int-gate
BX_CPU_THIS_PTR clear_IF ();
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_NT ();
BX_CPU_THIS_PTR clear_VM ();
BX_CPU_THIS_PTR clear_RF ();
if (!(gate_descriptor.type & 1)) // even is int-gate
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_NT();
BX_CPU_THIS_PTR clear_VM();
BX_CPU_THIS_PTR clear_RF();
return;
}
// else #GP(CS selector + ext)
BX_DEBUG(("interrupt: bad descriptor"));
BX_DEBUG(("c_ed=%u, descriptor.dpl=%u, CPL=%u",
(unsigned) cs_descriptor.u.segment.c_ed,
(unsigned) cs_descriptor.dpl,
BX_DEBUG(("type=%u, descriptor.dpl=%u, CPL=%u",
(unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl,
(unsigned) CPL));
BX_DEBUG(("cs.segment = %u", (unsigned) cs_descriptor.segment));
exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0);
@ -739,8 +734,7 @@ void BX_CPU_C::real_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
// real mode interrupt
Bit16u cs_selector, ip;
if ( (vector*4+3) > BX_CPU_THIS_PTR idtr.limit )
{
if ((vector*4+3) > BX_CPU_THIS_PTR idtr.limit) {
BX_ERROR(("interrupt(real mode) vector > idtr.limit"));
exception(BX_GP_EXCEPTION, 0, 0);
}
@ -758,12 +752,12 @@ void BX_CPU_C::real_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], cs_selector);
/* INT affects the following flags: I,T */
BX_CPU_THIS_PTR clear_IF ();
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_IF();
BX_CPU_THIS_PTR clear_TF();
#if BX_CPU_LEVEL >= 4
BX_CPU_THIS_PTR clear_AC ();
BX_CPU_THIS_PTR clear_AC();
#endif
BX_CPU_THIS_PTR clear_RF ();
BX_CPU_THIS_PTR clear_RF();
}
void BX_CPU_C::interrupt(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code)
@ -824,7 +818,7 @@ void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
#if BX_DEBUGGER
if (bx_guard.special_unwind_stack) {
BX_INFO(("exception() returning early because special_unwind_stack is set"));
BX_INFO(("exception(): returning early because special_unwind_stack is set"));
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
}
#endif
@ -863,7 +857,7 @@ void BX_CPU_C::exception(unsigned vector, Bit16u error_code, bx_bool is_INT)
shutdown();
}
#if BX_DEBUGGER
bx_guard.special_unwind_stack = true;
bx_guard.special_unwind_stack = 1;
#endif
longjmp(BX_CPU_THIS_PTR jmp_buf_env, 1); // go back to main decode loop
}

14
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.117 2006-06-11 21:37:22 sshwarts Exp $
// $Id: init.cc,v 1.118 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -784,12 +784,8 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; /* executable segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-confirming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0xFFFF0000;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFF;
@ -817,12 +813,8 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = 3; /* read/write/access */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = 0; /* data/stack segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = 0; /* normal expand up */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xFFFF;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xFFFF;

16
bochs/cpu/iret.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: iret.cc,v 1.14 2006-06-09 22:29:07 sshwarts Exp $
// $Id: iret.cc,v 1.15 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -285,10 +285,9 @@ BX_CPU_C::iret_protected(bxInstruction_c *i)
/* AR byte must indicate a writable data segment,
* else #GP(SS selector) */
if (ss_descriptor.valid==0 ||
ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable ||
ss_descriptor.u.segment.r_w==0)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("iret: SS AR byte not writable code segment"));
exception(BX_GP_EXCEPTION, raw_ss_selector & 0xfffc, 0);
@ -555,10 +554,9 @@ BX_CPU_C::long_iret(bxInstruction_c *i)
/* AR byte must indicate a writable data segment,
* else #GP(SS selector) */
if (ss_descriptor.valid==0 ||
ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable ||
ss_descriptor.u.segment.r_w==0)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("iret64: SS AR byte not writable code segment"));
exception(BX_GP_EXCEPTION, raw_ss_selector & 0xfffc, 0);

4
bochs/cpu/jmp_far.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: jmp_far.cc,v 1.6 2006-04-26 14:05:28 sshwarts Exp $
// $Id: jmp_far.cc,v 1.7 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -286,7 +286,7 @@ BX_CPU_C::jmp_call_gate64(bx_selector_t *gate_selector)
// AR byte of selected descriptor must indicate code segment,
// else #GP(code segment selector)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0)
IS_DATA_SEGMENT(cs_descriptor.type))
{
BX_ERROR(("jump_protected: not code segment in call gate 64"));
exception(BX_GP_EXCEPTION, dest_selector & 0xfffc, 0);

236
bochs/cpu/proc_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: proc_ctrl.cc,v 1.152 2006-06-11 21:37:22 sshwarts Exp $
// $Id: proc_ctrl.cc,v 1.153 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1082,19 +1082,15 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, 0x84c, 2, &limit);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base = (base_23_16 << 16) | base_15_0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit = limit;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = (access & 0x03); access >>= 2;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = (access & 0x01);
set_ar_byte(BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache, access);
if ( (BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value & 0xfffc) == 0 ) {
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value & 0xfffc) == 0) {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid==0 ||
else {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 1;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid==0 ||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment==0)
{
BX_PANIC(("loadall: DS invalid"));
@ -1112,18 +1108,15 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, 0x846, 2, &limit);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = (base_23_16 << 16) | base_15_0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = limit;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = (access & 0x03); access >>= 2;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = (access & 0x01);
set_ar_byte(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache, access);
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value & 0xfffc) == 0) {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 0;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid==0 ||
else {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid==0 ||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment==0)
{
BX_PANIC(("loadall: SS invalid"));
@ -1142,19 +1135,15 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, 0x840, 2, &limit);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = (base_23_16 << 16) | base_15_0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = limit;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = (access & 0x03); access >>= 2;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = (access & 0x01);
set_ar_byte(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache, access);
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value & 0xfffc) == 0)
{
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value & 0xfffc) == 0) {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 0;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid==0 ||
else {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid==0 ||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment==0)
{
BX_PANIC(("loadall: CS invalid"));
@ -1176,19 +1165,25 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, 0x83a, 2, &limit);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base = (base_23_16 << 16) | base_15_0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit = limit;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.a = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.r_w = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.executable = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = (access & 0x01); access >>= 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = (access & 0x03); access >>= 2;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.p = (access & 0x01);
set_ar_byte(BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache, access);
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value & 0xfffc) == 0) {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
}
else {
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 1;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid==0 ||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment==0)
{
BX_PANIC(("loadall: ES invalid"));
}
#if 0
BX_INFO(("cs.dpl = %02x", (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl));
BX_INFO(("ss.dpl = %02x", (unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl));
BX_INFO(("BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].dpl = %02x", (unsigned) BX_CPU_THIS_PTR ds.cache.dpl));
BX_INFO(("BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].dpl = %02x", (unsigned) BX_CPU_THIS_PTR es.cache.dpl));
BX_INFO(("BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].dpl = 0x%02x", (unsigned) BX_CPU_THIS_PTR ds.cache.dpl));
BX_INFO(("BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].dpl = 0x%02x", (unsigned) BX_CPU_THIS_PTR es.cache.dpl));
BX_INFO(("LOADALL: setting cs.selector.rpl to %u",
(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl));
BX_INFO(("LOADALL: setting ss.selector.rpl to %u",
@ -1199,16 +1194,6 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl));
#endif
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value & 0xfffc) == 0)
{
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0;
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid==0 ||
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment==0)
{
BX_PANIC(("loadall: ES invalid"));
}
/* DI */
BX_CPU_THIS_PTR mem->readPhysicalPage(BX_CPU_THIS, 0x826, 2, &di);
DI = di;
@ -1251,8 +1236,7 @@ void BX_CPU_C::LOADALL(bxInstruction_c *i)
#if 0
if (access)
BX_INFO(("LOADALL: GDTR access bits not 0 (%02x).",
(unsigned) access));
BX_INFO(("LOADALL: GDTR access bits not 0 (%02x)", (unsigned) access));
#endif
/* IDTR */
@ -1885,10 +1869,11 @@ void BX_CPU_C::SYSENTER(bxInstruction_c *i)
parse_selector(BX_CPU_THIS_PTR msr.sysenter_cs_msr & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
@ -1903,10 +1888,11 @@ void BX_CPU_C::SYSENTER(bxInstruction_c *i)
parse_selector((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 8) & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
@ -1943,10 +1929,11 @@ void BX_CPU_C::SYSEXIT(bxInstruction_c *i)
parse_selector((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 16) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; // code segment
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; // non-conforming
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; // readable
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; // accessed
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; // base address
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; // segment limit
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
@ -1961,10 +1948,11 @@ void BX_CPU_C::SYSEXIT(bxInstruction_c *i)
parse_selector((BX_CPU_THIS_PTR msr.sysenter_cs_msr + 24) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0; // data segment
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; // expand-up
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; // writeable
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; // accessed
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; // base address
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; // segment limit
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; // scaled segment limit
@ -2076,15 +2064,11 @@ SYSCALL_LEGACY_MODE:
parse_selector((MSR_STAR >> 32) & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-conforming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2101,15 +2085,11 @@ SYSCALL_LEGACY_MODE:
parse_selector(((MSR_STAR >> 32) + 8) & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = 3; /* read/write/access */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; /* normal expand up */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2132,15 +2112,11 @@ SYSCALL_LEGACY_MODE:
parse_selector((MSR_STAR >> 32) & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-conforming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2157,15 +2133,11 @@ SYSCALL_LEGACY_MODE:
parse_selector(((MSR_STAR >> 32) + 8) & BX_SELECTOR_RPL_MASK,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = 3; /* read/write/access */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0; /* normal expand up */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2259,15 +2231,11 @@ SYSRET_NON_64BIT_MODE:
parse_selector(((MSR_STAR >> 48) + 16) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-conforming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2283,15 +2251,11 @@ SYSRET_NON_64BIT_MODE:
parse_selector((MSR_STAR >> 48) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-conforming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2311,10 +2275,11 @@ SYSRET_NON_64BIT_MODE:
parse_selector((MSR_STAR >> 48) + 8,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
writeEFlags(R11, EFlagsValidMask);
@ -2325,15 +2290,11 @@ SYSRET_NON_64BIT_MODE:
parse_selector((MSR_STAR >> 48) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* non-conforming */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = 0; /* base address */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xFFFF; /* segment limit */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xFFFFFFFF; /* scaled segment limit */
@ -2350,10 +2311,11 @@ SYSRET_NON_64BIT_MODE:
parse_selector((MSR_STAR >> 48) + 8,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector);
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR assert_IF();
temp_RIP = ECX;

20
bochs/cpu/protect_ctrl.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: protect_ctrl.cc,v 1.47 2006-05-21 20:41:48 sshwarts Exp $
// $Id: protect_ctrl.cc,v 1.48 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -130,7 +130,7 @@ void BX_CPU_C::LAR_GvEw(bxInstruction_c *i)
*/
if (descriptor.segment) { /* normal segment */
if (descriptor.u.segment.executable && descriptor.u.segment.c_ed) {
if (IS_CODE_SEGMENT(descriptor.type) && IS_CODE_SEGMENT_CONFORMING(descriptor.type)) {
/* ignore DPL for conforming segments */
}
else {
@ -541,22 +541,24 @@ void BX_CPU_C::VERR_Ew(bxInstruction_c *i)
}
/* normal data/code segment */
if (descriptor.u.segment.executable) { /* code segment */
if (IS_CODE_SEGMENT(descriptor.type)) { /* code segment */
/* ignore DPL for readable conforming segments */
if (descriptor.u.segment.c_ed && descriptor.u.segment.r_w) {
if (IS_CODE_SEGMENT_CONFORMING(descriptor.type) &&
IS_CODE_SEGMENT_READABLE(descriptor.type))
{
BX_DEBUG(("VERR: conforming code, OK"));
assert_ZF(); /* accessible */
return;
}
if (descriptor.u.segment.r_w==0) {
if (!IS_CODE_SEGMENT_READABLE(descriptor.type)) {
BX_DEBUG(("VERR: code not readable"));
clear_ZF (); /* inaccessible */
clear_ZF(); /* inaccessible */
return;
}
/* readable, non-conforming code segment */
if ((descriptor.dpl<CPL) || (descriptor.dpl<selector.rpl)) {
BX_DEBUG(("VERR: non-conforming code not withing priv level"));
clear_ZF (); /* inaccessible */
clear_ZF(); /* inaccessible */
return;
}
@ -615,7 +617,7 @@ void BX_CPU_C::VERW_Ew(bxInstruction_c *i)
parse_descriptor(dword1, dword2, &descriptor);
/* rule out system segments & code segments */
if (descriptor.segment==0 || descriptor.u.segment.executable) {
if (descriptor.segment==0 || IS_CODE_SEGMENT(descriptor.type)) {
BX_DEBUG(("VERW: system seg or code"));
clear_ZF();
return;
@ -628,7 +630,7 @@ void BX_CPU_C::VERW_Ew(bxInstruction_c *i)
}
/* data segment */
if (descriptor.u.segment.r_w) { /* writable */
if (IS_DATA_SEGMENT_WRITEABLE(descriptor.type)) { /* writable */
if ((descriptor.dpl<CPL) || (descriptor.dpl<selector.rpl)) {
BX_DEBUG(("VERW: writable data seg not within priv level"));
clear_ZF(); /* not accessible */

6
bochs/cpu/ret_far.cc
View File

@ -1,5 +1,5 @@
////////////////////////////////////////////////////////////////////////
// $Id: ret_far.cc,v 1.6 2006-06-09 22:29:07 sshwarts Exp $
// $Id: ret_far.cc,v 1.7 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -259,8 +259,8 @@ BX_CPU_C::return_protected(bxInstruction_c *i, Bit16u pop_bytes)
/* descriptor AR byte must indicate a writable data segment,
* else #GP(selector) */
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable ||
ss_descriptor.u.segment.r_w==0)
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_ERROR(("return_protected: SS.AR byte not writable data"));
exception(BX_GP_EXCEPTION, raw_ss_selector & 0xfffc, 0);

96
bochs/cpu/segment_ctrl_pro.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: segment_ctrl_pro.cc,v 1.63 2006-06-09 22:29:07 sshwarts Exp $
// $Id: segment_ctrl_pro.cc,v 1.64 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -75,9 +75,8 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
}
/* AR byte must indicate a writable data segment else #GP(selector) */
if ((descriptor.segment==0) ||
descriptor.u.segment.executable ||
descriptor.u.segment.r_w==0 )
if (descriptor.segment==0 || IS_CODE_SEGMENT(descriptor.type) ||
IS_DATA_SEGMENT_WRITEABLE(descriptor.type) == 0)
{
BX_ERROR(("load_seg_reg(SS): not writable data segment"));
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
@ -144,9 +143,8 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
}
/* AR byte must indicate data or readable code segment else #GP(selector) */
if ( descriptor.segment==0 ||
(descriptor.u.segment.executable==1 &&
descriptor.u.segment.r_w==0) )
if (descriptor.segment==0 || (IS_CODE_SEGMENT(descriptor.type) &&
IS_CODE_SEGMENT_READABLE(descriptor.type) == 0))
{
BX_ERROR(("load_seg_reg(%s): not data or readable code", strseg(seg)));
exception(BX_GP_EXCEPTION, new_value & 0xfffc, 0);
@ -154,8 +152,8 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
/* If data or non-conforming code, then both the RPL and the CPL
* must be less than or equal to DPL in AR byte else #GP(selector) */
if (descriptor.u.segment.executable==0 ||
descriptor.u.segment.c_ed==0)
if (IS_DATA_SEGMENT(descriptor.type) ||
IS_CODE_SEGMENT_NON_CONFORMING(descriptor.type))
{
if ((selector.rpl > descriptor.dpl) || (CPL > descriptor.dpl)) {
BX_ERROR(("load_seg_reg(%s): RPL & CPL must be <= DPL", strseg(seg)));
@ -221,23 +219,20 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
seg->cache.p = 1; /* present */
if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
seg->cache.u.segment.executable = 1; /* code segment */
seg->cache.type = BX_CODE_EXEC_READ_ACCESSED;
#if BX_SUPPORT_ICACHE
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
invalidate_prefetch_q();
}
else {
seg->cache.u.segment.executable = 0; /* data segment */
seg->cache.type = BX_DATA_READ_WRITE_ACCESSED;
}
/* Do not modify segment limit and AR bytes when in real mode */
if (real_mode()) return;
seg->cache.dpl = 3; /* we are in v8086 mode */
seg->cache.u.segment.c_ed = 0; /* expand up */
seg->cache.u.segment.r_w = 1; /* writeable */
seg->cache.u.segment.a = 1; /* accessed */
seg->cache.u.segment.limit = 0xffff;
seg->cache.u.segment.limit_scaled = 0xffff;
#if BX_CPU_LEVEL >= 3
@ -287,8 +282,9 @@ void BX_CPU_C::validate_seg_reg(unsigned seg)
if (segment->cache.dpl < CPL)
{
// invalidate if data or non-conforming code segment
if ((segment->cache.valid==0) || (segment->cache.segment==0) ||
(segment->cache.u.segment.executable==0) || (segment->cache.u.segment.c_ed==0))
if (segment->cache.valid==0 || segment->cache.segment==0 ||
IS_DATA_SEGMENT(segment->cache.type) ||
IS_CODE_SEGMENT_NON_CONFORMING(segment->cache.type))
{
segment->selector.value = 0;
segment->cache.valid = 0;
@ -322,20 +318,10 @@ BX_CPU_C::ar_byte(const bx_descriptor_t *d)
return(0);
}
if (d->segment) {
return (d->u.segment.a) |
(d->u.segment.r_w << 1) |
(d->u.segment.c_ed << 2) |
(d->u.segment.executable << 3) |
(d->segment << 4) |
(d->dpl << 5) |
(d->p << 7);
}
else {
return (d->type) |
(d->dpl << 5) |
(d->p << 7);
}
return (d->type) |
(d->segment << 4) |
(d->dpl << 5) |
(d->p << 7);
}
void BX_CPP_AttrRegparmN(2)
@ -345,13 +331,6 @@ BX_CPU_C::set_ar_byte(bx_descriptor_t *d, Bit8u ar_byte)
d->dpl = (ar_byte >> 5) & 0x03;
d->segment = (ar_byte >> 4) & 0x01;
d->type = (ar_byte & 0x0f);
if (d->segment) {
d->u.segment.executable = (ar_byte >> 3) & 0x01;
d->u.segment.c_ed = (ar_byte >> 2) & 0x01;
d->u.segment.r_w = (ar_byte >> 1) & 0x01;
d->u.segment.a = (ar_byte >> 0) & 0x01;
}
}
Bit32u BX_CPP_AttrRegparmN(1)
@ -405,10 +384,7 @@ BX_CPU_C::get_descriptor_h(const bx_descriptor_t *d)
if (d->segment) {
val = (d->u.segment.base & 0xff000000) |
((d->u.segment.base >> 16) & 0x000000ff) |
(d->u.segment.executable << 11) |
(d->u.segment.c_ed << 10) |
(d->u.segment.r_w << 9) |
(d->u.segment.a << 8) |
(d->type << 8) |
(d->segment << 12) |
(d->dpl << 13) |
(d->p << 15) |
@ -471,10 +447,7 @@ BX_CPU_C::get_segment_ar_data(const bx_descriptor_t *d) // used for SMM
Bit16u val = 0;
if (d->segment) { /* data/code segment descriptors */
val = (d->u.segment.executable << 3) |
(d->u.segment.c_ed << 2) |
(d->u.segment.r_w << 1) |
(d->u.segment.a << 0) |
val = (d->type) |
(d->segment << 4) |
(d->dpl << 5) |
(d->p << 7) |
@ -491,13 +464,13 @@ BX_CPU_C::get_segment_ar_data(const bx_descriptor_t *d) // used for SMM
case BX_SYS_SEGMENT_LDT:
case BX_SYS_SEGMENT_AVAIL_286_TSS:
case BX_SYS_SEGMENT_BUSY_286_TSS:
val = (d->type << 0) |
val = (d->type) |
(d->dpl << 5) |
(d->p << 7);
return(val);
case BX_SYS_SEGMENT_AVAIL_386_TSS:
case BX_SYS_SEGMENT_BUSY_386_TSS:
val = (d->type << 0) |
val = (d->type) |
(d->dpl << 5) |
(d->p << 7) |
(d->u.tss.avl << 12) |
@ -523,22 +496,18 @@ bx_bool BX_CPU_C::set_segment_ar_data(bx_segment_reg_t *seg,
d->type = (ar_data & 0x0f);
if (d->segment) { /* data/code segment descriptors */
d->u.segment.executable = (ar_data >> 3) & 0x01;
d->u.segment.c_ed = (ar_data >> 2) & 0x01;
d->u.segment.r_w = (ar_data >> 1) & 0x01;
d->u.segment.a = (ar_data >> 0) & 0x01;
d->u.segment.g = (ar_data >> 15) & 0x01;
d->u.segment.d_b = (ar_data >> 14) & 0x01;
d->u.segment.g = (ar_data >> 15) & 0x01;
d->u.segment.d_b = (ar_data >> 14) & 0x01;
#if BX_SUPPORT_X86_64
d->u.segment.l = (ar_data >> 13) & 0x01;
d->u.segment.l = (ar_data >> 13) & 0x01;
#endif
d->u.segment.avl = (ar_data >> 12) & 0x01;
d->u.segment.avl = (ar_data >> 12) & 0x01;
d->u.segment.base = base;
d->u.segment.limit = limit;
d->u.segment.base = base;
d->u.segment.limit = limit;
if (d->u.segment.g) {
if ((d->u.segment.executable==0) && (d->u.segment.c_ed))
if (IS_DATA_SEGMENT(d->type) && IS_DATA_SEGMENT_EXPAND_DOWN(d->type))
d->u.segment.limit_scaled = (d->u.segment.limit << 12);
else
d->u.segment.limit_scaled = (d->u.segment.limit << 12) | 0x0fff;
@ -598,11 +567,6 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
temp->valid = 0; /* start out invalid */
if (temp->segment) { /* data/code segment descriptors */
temp->u.segment.executable = (AR_byte >> 3) & 0x01;
temp->u.segment.c_ed = (AR_byte >> 2) & 0x01;
temp->u.segment.r_w = (AR_byte >> 1) & 0x01;
temp->u.segment.a = (AR_byte >> 0) & 0x01;
temp->u.segment.limit = (dword1 & 0xffff);
temp->u.segment.base = (dword1 >> 16) | ((dword2 & 0xFF) << 16);
@ -617,7 +581,7 @@ BX_CPU_C::parse_descriptor(Bit32u dword1, Bit32u dword2, bx_descriptor_t *temp)
temp->u.segment.base |= (dword2 & 0xFF000000);
if (temp->u.segment.g) {
if ((temp->u.segment.executable==0) && (temp->u.segment.c_ed))
if (IS_DATA_SEGMENT(temp->type) && IS_DATA_SEGMENT_EXPAND_DOWN(temp->type))
temp->u.segment.limit_scaled = (temp->u.segment.limit << 12);
else
temp->u.segment.limit_scaled = (temp->u.segment.limit << 12) | 0x0fff;
@ -738,10 +702,10 @@ BX_CPU_C::load_ss(bx_selector_t *selector, bx_descriptor_t *descriptor, Bit8u cp
return;
}
#endif
if ( (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value & 0xfffc) == 0 )
if ((BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value & 0xfffc) == 0)
BX_PANIC(("load_ss(): null selector passed"));
if ( !BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid ) {
if (!BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid) {
BX_PANIC(("load_ss(): invalid selector/descriptor passed."));
}
}

20
bochs/cpu/smm.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: smm.cc,v 1.18 2006-06-11 21:37:22 sshwarts Exp $
// $Id: smm.cc,v 1.19 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2006 Stanislav Shwartsman
@ -46,11 +46,7 @@
// p - must be saved/restored
// dpl - must be saved/restored
// segment - must be 1 for seg registers, not required to save
// type - must be 0 for seg registers, not required to save
// executable - must be saved/restored
// c_ed - must be saved/restored
// r_w - must be saved/restored
// a - must be saved/restored
// type - must be saved/restored
// base - must be saved/restored
// limit - must be saved/restored
// g - must be saved/restored
@ -160,12 +156,8 @@ void BX_CPU_C::enter_system_management_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = 11; /* executable/readable/access code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; /* data/stack segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* normal expand up */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = BX_CPU_THIS_PTR smbase;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xffffffff;
@ -188,12 +180,8 @@ void BX_CPU_C::enter_system_management_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = 1; /* data/code segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = 3; /* read/write/access */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = 0; /* data/stack segment */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = 0; /* normal expand up */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = 1; /* writeable */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = 1; /* accessed */
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base = 0x00000000;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xffffffff;

6
bochs/cpu/stack32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: stack32.cc,v 1.32 2006-04-05 17:31:34 sshwarts Exp $
// $Id: stack32.cc,v 1.33 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -330,8 +330,8 @@ void BX_CPU_C::LEAVE(bxInstruction_c *i)
#endif
temp_EBP = BP;
if ( protected_mode() ) {
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed) { /* expand up */
if (protected_mode()) {
if (IS_DATA_SEGMENT_EXPAND_DOWN(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type)) {
if (temp_EBP <= BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled) {
BX_PANIC(("LEAVE: BP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].limit"));
exception(BX_SS_EXCEPTION, 0, 0);

9
bochs/cpu/stack_pro.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: stack_pro.cc,v 1.28 2006-05-12 17:04:19 sshwarts Exp $
// $Id: stack_pro.cc,v 1.29 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -225,7 +225,8 @@ BX_CPU_C::can_push(bx_descriptor_t *descriptor, Bit32u esp, Bit32u bytes)
return(0);
}
if (descriptor->u.segment.c_ed) { /* expand down segment */
if (IS_DATA_SEGMENT_EXPAND_DOWN(descriptor->type)) /* expand down segment */
{
Bit32u expand_down_limit;
if (descriptor->u.segment.d_b)
@ -316,7 +317,7 @@ bx_bool BX_CPU_C::can_pop(Bit32u bytes)
return(0);
}
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed) { /* expand down segment */
if (IS_DATA_SEGMENT_EXPAND_DOWN(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type)) { /* expand down */
if (temp_ESP == expand_down_limit) {
BX_PANIC(("can_pop(): found SP=ffff"));
return(0);
@ -334,7 +335,7 @@ bx_bool BX_CPU_C::can_pop(Bit32u bytes)
BX_PANIC(("can_pop(): found SP=ffff"));
return(0);
}
if ( temp_ESP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled ) {
if (temp_ESP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled) {
BX_PANIC(("can_pop(): eSP > SS.limit"));
return(0);
}

38
bochs/cpu/tasking.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: tasking.cc,v 1.34 2006-06-09 22:29:07 sshwarts Exp $
// $Id: tasking.cc,v 1.35 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -557,7 +557,7 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// CS descriptor AR byte must indicate code segment else #TS(CS)
if (cs_descriptor.valid==0 || cs_descriptor.segment==0 ||
cs_descriptor.u.segment.executable==0)
IS_DATA_SEGMENT(cs_descriptor.type))
{
BX_PANIC(("task_switch: CS not valid executable seg"));
exception_no = BX_TS_EXCEPTION;
@ -566,8 +566,8 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
}
// if non-conforming then DPL must equal selector RPL else #TS(CS)
if (cs_descriptor.u.segment.c_ed==0 &&
cs_descriptor.dpl!=cs_selector.rpl)
if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) &&
cs_descriptor.dpl != cs_selector.rpl)
{
BX_INFO(("task_switch: non-conforming: CS.dpl!=CS.RPL"));
exception_no = BX_TS_EXCEPTION;
@ -576,8 +576,8 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
}
// if conforming then DPL must be <= selector RPL else #TS(CS)
if (cs_descriptor.u.segment.c_ed &&
cs_descriptor.dpl>cs_selector.rpl)
if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) &&
cs_descriptor.dpl > cs_selector.rpl)
{
BX_INFO(("task_switch: conforming: CS.dpl>RPL"));
exception_no = BX_TS_EXCEPTION;
@ -624,8 +624,8 @@ void BX_CPU_C::task_switch(bx_selector_t *tss_selector,
// SS descriptor AR byte must must indicate writable data segment,
// else #TS(SS)
if (ss_descriptor.valid==0 || ss_descriptor.segment==0 ||
ss_descriptor.u.segment.executable ||
ss_descriptor.u.segment.r_w==0)
IS_CODE_SEGMENT(ss_descriptor.type) ||
!IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type))
{
BX_INFO(("task_switch: SS not valid"));
exception_no = BX_TS_EXCEPTION;
@ -706,7 +706,7 @@ void BX_CPU_C::task_switch_load_selector(bx_segment_reg_t *seg,
Bit32u dword1, dword2;
// NULL selector is OK, will leave cache invalid
if ( (raw_selector & 0xfffc) != 0 )
if ((raw_selector & 0xfffc) != 0)
{
bx_bool good = fetch_raw_descriptor2(selector, &dword1, &dword2);
if (!good) {
@ -716,19 +716,23 @@ void BX_CPU_C::task_switch_load_selector(bx_segment_reg_t *seg,
parse_descriptor(dword1, dword2, &descriptor);
if (descriptor.valid==0 || descriptor.segment==0 ||
(descriptor.u.segment.executable &&
descriptor.u.segment.r_w==0))
/* AR byte must indicate data or readable code segment else #TS(selector) */
if (descriptor.segment==0 || (IS_CODE_SEGMENT(descriptor.type) &&
IS_CODE_SEGMENT_READABLE(descriptor.type) == 0))
{
BX_ERROR(("task_switch(%s): not a writeable data segment !", strseg(seg)));
BX_ERROR(("task_switch(%s): not data or readable code !", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
}
if (descriptor.type < 12 &&
(descriptor.dpl < cs_rpl || descriptor.dpl < selector->rpl))
/* If data or non-conforming code, then both the RPL and the CPL
* must be less than or equal to DPL in AR byte else #GP(selector) */
if (IS_DATA_SEGMENT(descriptor.type) ||
IS_CODE_SEGMENT_NON_CONFORMING(descriptor.type))
{
BX_ERROR(("task_switch(%s): descriptor DPL check failed !", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
if ((selector->rpl > descriptor.dpl) || (cs_rpl > descriptor.dpl)) {
BX_ERROR(("load_seg_reg(%s): RPL & CPL must be <= DPL", strseg(seg)));
exception(BX_TS_EXCEPTION, raw_selector & 0xfffc, 0);
}
}
if (! IS_PRESENT(descriptor)) {

97
bochs/cpu/vm8086.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: vm8086.cc,v 1.26 2006-03-27 18:02:07 sshwarts Exp $
// $Id: vm8086.cc,v 1.27 2006-06-12 16:58:27 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -225,8 +225,8 @@ void BX_CPU_C::v86_redirect_interrupt(Bit32u vector)
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS], (Bit16u) temp_CS);
RIP = temp_IP;
BX_CPU_THIS_PTR clear_TF ();
BX_CPU_THIS_PTR clear_RF ();
BX_CPU_THIS_PTR clear_TF();
BX_CPU_THIS_PTR clear_RF();
if (BX_CPU_THIS_PTR get_IOPL() == 3)
BX_CPU_THIS_PTR clear_IF ();
else
@ -236,15 +236,13 @@ void BX_CPU_C::v86_redirect_interrupt(Bit32u vector)
void BX_CPU_C::init_v8086_mode(void)
{
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.type = BX_CODE_EXEC_READ_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xffff;
@ -257,15 +255,12 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR updateFetchModeMask();
#endif
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.limit_scaled = 0xffff;
@ -274,15 +269,12 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.rpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.limit_scaled = 0xffff;
@ -291,15 +283,12 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.rpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.limit_scaled = 0xffff;
@ -308,15 +297,12 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.rpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.limit_scaled = 0xffff;
@ -325,15 +311,12 @@ void BX_CPU_C::init_v8086_mode(void)
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.avl = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.rpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.executable = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.c_ed = 0;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.r_w = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.a = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.p = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.dpl = 3;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.segment = 1;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.type = BX_DATA_READ_WRITE_ACCESSED;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base =
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value << 4;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit = 0xffff;
BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled = 0xffff;