Fix compilation errors
Add BX_INFO for writing to TSC_MSR (not implemented message)
This commit is contained in:
Stanislav Shwartsman
parent
caa0648188
commit
8482511af3
2
bochs/configure
vendored
2
bochs/configure
vendored
@ -34627,7 +34627,7 @@ _ACEOF
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fi
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else
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if test "$bx_cpu_level" -gt 5; then
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if test "$bx_cpu_level" -gt 4; then
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echo "$as_me:$LINENO: result: yes" >&5
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echo "${ECHO_T}yes" >&6
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cat >>confdefs.h <<\_ACEOF
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@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script.
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AC_PREREQ(2.50)
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AC_INIT(bochs.h)
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AC_REVISION([[$Id: configure.in,v 1.278 2005-04-16 07:32:58 vruppert Exp $]])
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AC_REVISION([[$Id: configure.in,v 1.279 2005-04-18 17:21:32 sshwarts Exp $]])
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AC_CONFIG_HEADER(config.h)
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AC_CONFIG_HEADER(ltdlconf.h)
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@ -922,7 +922,7 @@ AC_ARG_ENABLE(4meg-pages,
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AC_DEFINE(BX_SUPPORT_4MEG_PAGES, 0)
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fi],
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[
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if test "$bx_cpu_level" -gt 5; then
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if test "$bx_cpu_level" -gt 4; then
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AC_MSG_RESULT(yes)
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AC_DEFINE(BX_SUPPORT_4MEG_PAGES, 1)
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else
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@ -1,8 +1,11 @@
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#ifndef EXTDB_H
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#define EXTDB_H
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typedef struct {
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Bit64u base;
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Bit16u limit;
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Bit16u fill[3];
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} descbase;
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} descbase;
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typedef struct {
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Bit64u rax,rcx,rdx,rbx,rsp,rbp,rsi,rdi,
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@ -19,7 +22,7 @@ typedef struct {
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#define debug_run 1
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#define debug_count 2
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#define debug_skip 3
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} TRegs;
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} TRegs;
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extern TRegs regs;
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@ -27,3 +30,4 @@ extern char debug_loaded;
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void bx_external_debugger(BX_CPU_C *cpu);
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.101 2005-03-30 20:53:00 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.102 2005-04-18 17:21:33 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1569,10 +1569,6 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i)
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/* TODO */
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return;
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case BX_MSR_TSC:
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RDTSC(i);
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return;
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case BX_MSR_CESR:
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/* TODO */
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return;
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@ -1583,10 +1579,6 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i)
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/* do nothing */
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return;
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case BX_MSR_TSC:
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RDTSC(i);
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return;
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/* ... And these cause an exception on i686 */
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case BX_MSR_CESR:
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case BX_MSR_CTR0:
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@ -1594,6 +1586,10 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i)
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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case BX_MSR_TSC:
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RDTSC(i);
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return;
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/* MSR_APICBASE
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0:7 Reserved
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8 This is set if its the BSP
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@ -1705,7 +1701,6 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
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/* The following registers are defined for Pentium only */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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case BX_MSR_TSC:
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case BX_MSR_CESR:
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/* TODO */
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return;
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@ -1713,7 +1708,6 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
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/* These are noops on i686... */
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case BX_MSR_P5_MC_ADDR:
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case BX_MSR_MC_TYPE:
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case BX_MSR_TSC:
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/* do nothing */
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return;
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@ -1724,9 +1718,13 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
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goto do_exception;
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#endif /* BX_CPU_LEVEL == 5 */
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case BX_MSR_TSC:
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BX_INFO("WRMSR: writing to BX_MSR_TSC still not implemented");
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return;
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/* MSR_APICBASE
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0:7 Reserved
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8 This is set if its the BSP
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8 This is set if its the BSP
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9:10 Reserved
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11 APIC Global Enable bit (1=enabled 0=disabled)
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12:35 APIC Base Address
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@ -1750,8 +1748,8 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
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case BX_MSR_EFER:
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// GPF #0 if lme 0->1 and cr0.pg = 1
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// GPF #0 if lme 1->0 and cr0.pg = 1
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if ((BX_CPU_THIS_PTR msr.lme != ((EAX >> 8) & 1))
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&& (BX_CPU_THIS_PTR cr0.pg == 1))
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if ((BX_CPU_THIS_PTR msr.lme != ((EAX >> 8) & 1)) &&
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(BX_CPU_THIS_PTR cr0.pg == 1))
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{
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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@ -1759,16 +1757,16 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i)
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BX_CPU_THIS_PTR msr.lme = (EAX >> 8) & 1;
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return;
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case BX_MSR_STAR:
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MSR_STAR = ((Bit64u) EDX << 32) + EAX;
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MSR_STAR = ((Bit64u) EDX << 32) + EAX;
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return;
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case BX_MSR_LSTAR:
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MSR_LSTAR = ((Bit64u) EDX << 32) + EAX;
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MSR_LSTAR = ((Bit64u) EDX << 32) + EAX;
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return;
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case BX_MSR_CSTAR:
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MSR_CSTAR = ((Bit64u) EDX << 32) + EAX;
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MSR_CSTAR = ((Bit64u) EDX << 32) + EAX;
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return;
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case BX_MSR_FMASK:
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MSR_FMASK = ((Bit64u) EDX << 32) + EAX;
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MSR_FMASK = ((Bit64u) EDX << 32) + EAX;
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return;
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case BX_MSR_FSBASE:
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MSR_FSBASE = ((Bit64u) EDX << 32) + EAX;
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@ -2230,25 +2228,25 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
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(laddr_0 <= dr0_n) &&
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(laddr_n >= dr0) )
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ibpoint_found = 1;
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}
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}
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if ( (dr7 & 0x0000000c) ) {
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if ( (dr1_op==opa || dr1_op==opb) &&
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(laddr_0 <= dr1_n) &&
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(laddr_n >= dr1) )
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ibpoint_found = 1;
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}
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}
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if ( (dr7 & 0x00000030) ) {
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if ( (dr2_op==opa || dr2_op==opb) &&
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(laddr_0 <= dr2_n) &&
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(laddr_n >= dr2) )
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ibpoint_found = 1;
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}
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}
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if ( (dr7 & 0x000000c0) ) {
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if ( (dr3_op==opa || dr3_op==opb) &&
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(laddr_0 <= dr3_n) &&
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(laddr_n >= dr3) )
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ibpoint_found = 1;
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}
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}
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// If *any* enabled breakpoints matched, then we need to
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// set status bits for *all* breakpoints, even disabled ones,
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@ -2277,7 +2275,7 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size,
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(laddr_n >= dr3) )
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dr6_mask |= 0x08;
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return(dr6_mask);
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}
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}
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return(0);
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.h,v 1.15 2005-03-17 20:50:57 sshwarts Exp $
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// $Id: instrument.h,v 1.16 2005-04-18 17:21:34 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -94,9 +94,9 @@ void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval);
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void bx_instr_cache_cntrl(unsigned cpu, unsigned what);
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void bx_instr_prefetch_hint(unsigned cpu, unsigned what, unsigned seg, bx_address offset);
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void bx_instr_before_execution(unsigned cpu);
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void bx_instr_after_execution(unsigned cpu);
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void bx_instr_repeat_iteration(unsigned cpu);
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void bx_instr_before_execution(unsigned cpu, const bxInstruction_c *i);
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void bx_instr_after_execution(unsigned cpu, const bxInstruction_c *i);
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void bx_instr_repeat_iteration(unsigned cpu, const bxInstruction_c *i);
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void bx_instr_inp(Bit16u addr, unsigned len);
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void bx_instr_outp(Bit16u addr, unsigned len);
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