From 8482511af39f271170040a279e6ad2bcf08c5eaf Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Mon, 18 Apr 2005 17:21:34 +0000 Subject: [PATCH] Fix compilation errors Add BX_INFO for writing to TSC_MSR (not implemented message) --- bochs/configure | 2 +- bochs/configure.in | 4 +-- bochs/cpu/extdb.h | 8 ++++-- bochs/cpu/proc_ctrl.cc | 44 ++++++++++++++--------------- bochs/instrument/stubs/instrument.h | 8 +++--- 5 files changed, 34 insertions(+), 32 deletions(-) diff --git a/bochs/configure b/bochs/configure index cc4c4e479..b0468ba5a 100755 --- a/bochs/configure +++ b/bochs/configure @@ -34627,7 +34627,7 @@ _ACEOF fi else - if test "$bx_cpu_level" -gt 5; then + if test "$bx_cpu_level" -gt 4; then echo "$as_me:$LINENO: result: yes" >&5 echo "${ECHO_T}yes" >&6 cat >>confdefs.h <<\_ACEOF diff --git a/bochs/configure.in b/bochs/configure.in index ffca320db..ea03c085c 100644 --- a/bochs/configure.in +++ b/bochs/configure.in @@ -2,7 +2,7 @@ dnl // Process this file with autoconf to produce a configure script. AC_PREREQ(2.50) AC_INIT(bochs.h) -AC_REVISION([[$Id: configure.in,v 1.278 2005-04-16 07:32:58 vruppert Exp $]]) +AC_REVISION([[$Id: configure.in,v 1.279 2005-04-18 17:21:32 sshwarts Exp $]]) AC_CONFIG_HEADER(config.h) AC_CONFIG_HEADER(ltdlconf.h) @@ -922,7 +922,7 @@ AC_ARG_ENABLE(4meg-pages, AC_DEFINE(BX_SUPPORT_4MEG_PAGES, 0) fi], [ - if test "$bx_cpu_level" -gt 5; then + if test "$bx_cpu_level" -gt 4; then AC_MSG_RESULT(yes) AC_DEFINE(BX_SUPPORT_4MEG_PAGES, 1) else diff --git a/bochs/cpu/extdb.h b/bochs/cpu/extdb.h index 9816b21f1..8c2396fb2 100644 --- a/bochs/cpu/extdb.h +++ b/bochs/cpu/extdb.h @@ -1,8 +1,11 @@ +#ifndef EXTDB_H +#define EXTDB_H + typedef struct { Bit64u base; Bit16u limit; Bit16u fill[3]; - } descbase; +} descbase; typedef struct { Bit64u rax,rcx,rdx,rbx,rsp,rbp,rsi,rdi, @@ -19,7 +22,7 @@ typedef struct { #define debug_run 1 #define debug_count 2 #define debug_skip 3 - } TRegs; +} TRegs; extern TRegs regs; @@ -27,3 +30,4 @@ extern char debug_loaded; void bx_external_debugger(BX_CPU_C *cpu); +#endif diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc index f015c12e8..ba6ec9919 100644 --- a/bochs/cpu/proc_ctrl.cc +++ b/bochs/cpu/proc_ctrl.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: proc_ctrl.cc,v 1.101 2005-03-30 20:53:00 sshwarts Exp $ +// $Id: proc_ctrl.cc,v 1.102 2005-04-18 17:21:33 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -1569,10 +1569,6 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i) /* TODO */ return; - case BX_MSR_TSC: - RDTSC(i); - return; - case BX_MSR_CESR: /* TODO */ return; @@ -1583,10 +1579,6 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i) /* do nothing */ return; - case BX_MSR_TSC: - RDTSC(i); - return; - /* ... And these cause an exception on i686 */ case BX_MSR_CESR: case BX_MSR_CTR0: @@ -1594,6 +1586,10 @@ void BX_CPU_C::RDMSR(bxInstruction_c *i) goto do_exception; #endif /* BX_CPU_LEVEL == 5 */ + case BX_MSR_TSC: + RDTSC(i); + return; + /* MSR_APICBASE 0:7 Reserved 8 This is set if its the BSP @@ -1705,7 +1701,6 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i) /* The following registers are defined for Pentium only */ case BX_MSR_P5_MC_ADDR: case BX_MSR_MC_TYPE: - case BX_MSR_TSC: case BX_MSR_CESR: /* TODO */ return; @@ -1713,7 +1708,6 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i) /* These are noops on i686... */ case BX_MSR_P5_MC_ADDR: case BX_MSR_MC_TYPE: - case BX_MSR_TSC: /* do nothing */ return; @@ -1724,9 +1718,13 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i) goto do_exception; #endif /* BX_CPU_LEVEL == 5 */ + case BX_MSR_TSC: + BX_INFO("WRMSR: writing to BX_MSR_TSC still not implemented"); + return; + /* MSR_APICBASE 0:7 Reserved - 8 This is set if its the BSP + 8 This is set if its the BSP 9:10 Reserved 11 APIC Global Enable bit (1=enabled 0=disabled) 12:35 APIC Base Address @@ -1750,8 +1748,8 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i) case BX_MSR_EFER: // GPF #0 if lme 0->1 and cr0.pg = 1 // GPF #0 if lme 1->0 and cr0.pg = 1 - if ((BX_CPU_THIS_PTR msr.lme != ((EAX >> 8) & 1)) - && (BX_CPU_THIS_PTR cr0.pg == 1)) + if ((BX_CPU_THIS_PTR msr.lme != ((EAX >> 8) & 1)) && + (BX_CPU_THIS_PTR cr0.pg == 1)) { exception(BX_GP_EXCEPTION, 0, 0); } @@ -1759,16 +1757,16 @@ void BX_CPU_C::WRMSR(bxInstruction_c *i) BX_CPU_THIS_PTR msr.lme = (EAX >> 8) & 1; return; case BX_MSR_STAR: - MSR_STAR = ((Bit64u) EDX << 32) + EAX; + MSR_STAR = ((Bit64u) EDX << 32) + EAX; return; case BX_MSR_LSTAR: - MSR_LSTAR = ((Bit64u) EDX << 32) + EAX; + MSR_LSTAR = ((Bit64u) EDX << 32) + EAX; return; case BX_MSR_CSTAR: - MSR_CSTAR = ((Bit64u) EDX << 32) + EAX; + MSR_CSTAR = ((Bit64u) EDX << 32) + EAX; return; case BX_MSR_FMASK: - MSR_FMASK = ((Bit64u) EDX << 32) + EAX; + MSR_FMASK = ((Bit64u) EDX << 32) + EAX; return; case BX_MSR_FSBASE: MSR_FSBASE = ((Bit64u) EDX << 32) + EAX; @@ -2230,25 +2228,25 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size, (laddr_0 <= dr0_n) && (laddr_n >= dr0) ) ibpoint_found = 1; - } + } if ( (dr7 & 0x0000000c) ) { if ( (dr1_op==opa || dr1_op==opb) && (laddr_0 <= dr1_n) && (laddr_n >= dr1) ) ibpoint_found = 1; - } + } if ( (dr7 & 0x00000030) ) { if ( (dr2_op==opa || dr2_op==opb) && (laddr_0 <= dr2_n) && (laddr_n >= dr2) ) ibpoint_found = 1; - } + } if ( (dr7 & 0x000000c0) ) { if ( (dr3_op==opa || dr3_op==opb) && (laddr_0 <= dr3_n) && (laddr_n >= dr3) ) ibpoint_found = 1; - } + } // If *any* enabled breakpoints matched, then we need to // set status bits for *all* breakpoints, even disabled ones, @@ -2277,7 +2275,7 @@ Bit32u BX_CPU_C::hwdebug_compare(Bit32u laddr_0, unsigned size, (laddr_n >= dr3) ) dr6_mask |= 0x08; return(dr6_mask); - } + } return(0); } diff --git a/bochs/instrument/stubs/instrument.h b/bochs/instrument/stubs/instrument.h index 57decb3a7..7a858d224 100644 --- a/bochs/instrument/stubs/instrument.h +++ b/bochs/instrument/stubs/instrument.h @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: instrument.h,v 1.15 2005-03-17 20:50:57 sshwarts Exp $ +// $Id: instrument.h,v 1.16 2005-04-18 17:21:34 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (C) 2001 MandrakeSoft S.A. @@ -94,9 +94,9 @@ void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, Bit32u newval); void bx_instr_cache_cntrl(unsigned cpu, unsigned what); void bx_instr_prefetch_hint(unsigned cpu, unsigned what, unsigned seg, bx_address offset); -void bx_instr_before_execution(unsigned cpu); -void bx_instr_after_execution(unsigned cpu); -void bx_instr_repeat_iteration(unsigned cpu); +void bx_instr_before_execution(unsigned cpu, const bxInstruction_c *i); +void bx_instr_after_execution(unsigned cpu, const bxInstruction_c *i); +void bx_instr_repeat_iteration(unsigned cpu, const bxInstruction_c *i); void bx_instr_inp(Bit16u addr, unsigned len); void bx_instr_outp(Bit16u addr, unsigned len);