Fix another broking change
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.134 2006-03-02 17:39:10 sshwarts Exp $
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// $Id: cpu.cc,v 1.135 2006-03-04 09:22:54 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -227,7 +227,6 @@ void BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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if (BX_CPU_THIS_PTR trace) {
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// print the instruction that is about to be executed.
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bx_dbg_disassemble_current(BX_CPU_ID, 1); // only one cpu, print time stamp
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}
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#endif
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// decoding instruction compeleted -> continue with execution
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@ -740,8 +739,8 @@ void BX_CPU_C::prefetch(void)
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if (! Is64BitMode()) {
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Bit32u temp_limit = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled;
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if (((Bit32u) temp_rip) >= temp_limit) {
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BX_ERROR(("prefetch: EIP > CS.limit"));
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if (((Bit32u) temp_rip) > temp_limit) {
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BX_ERROR(("prefetch: EIP [%08x] > CS.limit [%08x]", (Bit32u) temp_rip, temp_limit));
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exception(BX_GP_EXCEPTION, 0, 0);
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: proc_ctrl.cc,v 1.137 2006-03-01 22:32:24 sshwarts Exp $
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// $Id: proc_ctrl.cc,v 1.138 2006-03-04 09:22:55 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -601,13 +601,11 @@ void BX_CPU_C::MOV_CdRd(bxInstruction_c *i)
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BX_PANIC(("MOV_CdRd: CR1 not implemented yet"));
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break;
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case 2: /* CR2 */
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BX_DEBUG(("MOV_CdRd: CR2 not implemented yet"));
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BX_DEBUG(("MOV_CdRd: CR2 = reg"));
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BX_DEBUG(("MOV_CdRd:CR2 = %08x", (unsigned) val_32));
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BX_CPU_THIS_PTR cr2 = val_32;
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break;
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case 3: // CR3
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if (bx_dbg.creg)
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BX_INFO(("MOV_CdRd:CR3 = %08x", (unsigned) val_32));
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BX_DEBUG(("MOV_CdRd:CR3 = %08x", (unsigned) val_32));
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// Reserved bits take on value of MOV instruction
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CR3_change(val_32);
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BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_32);
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@ -661,25 +659,17 @@ void BX_CPU_C::MOV_RdCd(bxInstruction_c *i)
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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val_32 = BX_CPU_THIS_PTR cr0.val32;
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#if 0
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BX_INFO(("MOV_RdCd:CR0: R32 = %08x @CS:EIP %04x:%04x",
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(unsigned) val_32,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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(unsigned) EIP));
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#endif
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break;
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case 1: /* CR1 */
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BX_PANIC(("MOV_RdCd: CR1 not implemented yet"));
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val_32 = 0;
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break;
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case 2: /* CR2 */
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if (bx_dbg.creg)
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BX_INFO(("MOV_RdCd: CR2"));
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BX_DEBUG(("MOV_RdCd: reading CR3"));
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val_32 = BX_CPU_THIS_PTR cr2;
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break;
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case 3: // CR3
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if (bx_dbg.creg)
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BX_INFO(("MOV_RdCd: reading CR3"));
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BX_DEBUG(("MOV_RdCd: reading CR3"));
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val_32 = BX_CPU_THIS_PTR cr3;
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break;
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case 4: // CR4
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@ -745,12 +735,11 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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BX_PANIC(("MOV_CqRq: CR1 not implemented yet"));
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break;
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case 2: /* CR2 */
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BX_DEBUG(("MOV_CqRq: CR2 not implemented yet"));
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BX_CPU_THIS_PTR cr2 = val_64;
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break;
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case 3: // CR3
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if (bx_dbg.creg)
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BX_INFO(("MOV_CqRq:CR3 = %08x", (unsigned) val_64));
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BX_INFO(("MOV_CqRq: write to CR3 of %08x:%08x",
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(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
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// Reserved bits take on value of MOV instruction
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CR3_change(val_64);
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BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_MOV_CR3, val_64);
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@ -758,7 +747,7 @@ void BX_CPU_C::MOV_CqRq(bxInstruction_c *i)
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case 4: // CR4
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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BX_INFO(("MOV_CqRq: write to CR4 of %08x:%08x",
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BX_DEBUG(("MOV_CqRq: write to CR4 of %08x:%08x",
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(Bit32u)(val_64 >> 32), (Bit32u)(val_64 & 0xFFFFFFFF)));
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SetCR4(val_64);
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break;
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@ -809,12 +798,6 @@ void BX_CPU_C::MOV_RqCq(bxInstruction_c *i)
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switch (i->nnn()) {
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case 0: // CR0 (MSW)
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val_64 = BX_CPU_THIS_PTR cr0.val32;
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#if 0
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BX_INFO(("MOV_RqCq:CR0: R64 = %08x @CS:EIP %04x:%04x",
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(unsigned) val_64,
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(unsigned) BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value,
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(unsigned) EIP));
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#endif
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break;
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case 1: /* CR1 */
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BX_PANIC(("MOV_RqCq: CR1 not implemented yet"));
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