* PCI ID's from Linux
* There are a bunch of NAVI quirks around 3d rendering pipelines
but not many around modesetting (which is the only thing we care
about)
Change-Id: If63e31fe1d37d9d95f2a71c222a4cda7a2914a5e
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4467
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Change-Id: Ifbd82ef7bfc2c39b2aeb5c25be177421cd22d246
Reviewed-on: https://review.haiku-os.org/c/haiku/+/2920
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
- Cleanup HEAD_MODE constants. These should be completely removed, now
that we have a proper notion of pipes and displays. But the DPMS code
still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
missing a +1 to show the actual videomode values
We need to assign PLLs to pipes and transcoders. The assignments on
previous generations were fixed, but now it's up to us to set it up.
Do the simplest thing for now: assign PLL1 to pipe A and PLL2 to pipe B.
- 7xx (1st gen) has no driver in Haiku or is handled by the intel_810 driver
- PowerVR has no driver in Haiku
So there is no point in having those in the intel_extreme driver.
While I'm at it, fix the video timing/resolution constraints for
sanitize_video_mode.
- The name for the registers were swapped
- The width and height were also swapped in one of them
- Remove some old #if 0 code that touched these registers but has been
disabled for a while.
LVDS panels must really be driven at their native resolution, otherwise
they will simply not work. This means we should basically never touch
the video timings on that side. We need to only set the source size in
the pipe configuration, and let the panel fitter figure out the scaling.
On my G45 laptop, this allows me to use non-native resolutions on the
laptop display. This also means when booting with a VGA display
connected, I do get a valid display on the internal panel (using the VGA
resolution). VGA still gets "out of range", so we're still not setting
up something there.
If I switch to VGA display in the BIOS, I get a working picture there
and garbage on the internal display, which is progress (before I would
get a black screen on the internal display)
Fixes#12723.
- Remove duplicate and otherwise unused lendian_bitfield.h
- Adjust listusb jamfile to use lendian_bitfield.h
- Fix various typos in usb_video.h and restore some fields to make
listusb happy
This reverts commit 4f059c1fc5.
From discussion on the mailing list, it seems I was correct the first time
and Broadwell is Gen8. The confusion comes from the SER5/SOC distinction,
which is not in the Linux driver, and I still don't know which one it really
belongs in.
* GCC7's static analysis found this one and it still
took #gcc and me a while to spot. Nice work gcc7!
* Should help DisplayPort training issues :-)
Change-Id: I9b47f13c95e622a2c08ff329ec9c3fc7e3db493d
At present, does not work (it fails to properly set up interrupts,
resulting in thousands of unhandled ones which all but grinds the system
to a halt) but this at least is some progress.
Accelerant interface:
Introduce new hooks B_SET_BRIGHTNESS and B_GET_BRIGHTNESS. Brightness is
a float in the 0..1 range.
App_server:
Forward brightness things between BScreen and the accelerant.
intel_extreme:
Implement the hooks. Note that this only works for laptop panels, but
the driver will pretend to support it in other cases as well.
Screen preferences:
If the accelerant supports the B_GET_BRIGHTNESS hook, allow to set
brightness with a slider. Otherwise, the slidere is hidden and these
changes aren't visible.
Was nothing but a slightly-stripped version of the nvidia driver,
not touched substantially in nearly 10 years, and the cards it was
originally going to support (but never got anywhere near so) have long since
been deprecated.
* Caching these values could result in missed
state changes.
* We may want to re-implement later.
* Highlights that all DP AUX communication is broken
during my testing.
* Now pulling in latest amdgpu atombios.h headers
* Lots of DisplayPort cleanup and removal of legacy stuff
* Add obsolete atombios header for things that disappear
(amdgpu doesn't support older cards like we do)
* Introduce new code to support later encoder tables
* Drop radeon-specific encoder service from common dp_info
* Tested on HD 5450 hdmi
* Helps prevent mainboard explosions and other bad stuff.
* ...maybe not explosions, but bad things.
* The RX 480 reference design can pull as much as 90W
from its PCIe slot at load. PCIe is rated for 75W.
* This change overloads the PCIe power cables vs the PCIe
slot. The PCIe power cables can handle going over spec.
* Untested since we really can't come close to loading a
RX 480 without hardware OpenGL ^_^
* Should be able to test on real hardware within a week.
There was some mixup with the interrupt registers, still:
- The driver uses 16-bit read/write, but on SandyBridge the register is
32 bits
- There is a global interrupt enable bit, which must be set to unmask
everything else
- The bits for vblank interrupt are not the same on SNB and later PCH
based devices, and the code mixed the two.
Move the computation of the interrupt bits to an helper function, and
use it everywhere to make sure we always use the right bits.
Modesetting
===========
My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:
- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed
DPMS
====
It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.
Remaining hacks
===============
I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.
This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.
* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.
* Move current_mode into the accelerant as the
driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
Mode set should notice that and fall back to panel_mode
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.
* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
likely need broken apart.
* No impact to non-ValleyView chipsets
* Bump some register locations for VLV
* Only have HDMI port to test with on my ValleyView GPU
and our driver seems to be missing all HDMI and
sideband functionality.
* As ValleyView chipsets seem to be UEFI only, we don't
have VESA fallback, so this shouldn't cause regressions.
(unless we get UEFI framebuffer support)
Intel changed the PCH interrupt bits between Sandy Bridge and Ivy Bridge
to make space for the 3rd display pipe. Take this into account and check
for the correct bits on the newer devices.
Fixes#11522.
* These aren't tested, but since we go off of DCE
versions for a lot of stuff, they may work.
* AMD doens't include market names in their drivers
anymore, so if we want to label them it will take
additional work.
* This is less pretty, but we need access to the connector
to find the HPD gpio pin mask on the card.
* dp_aux communications seem to work again.
* If you have a DisplayPort item attached to your card you
may want to just unplug it at this point. We attempt DP
link training and it fails. This failure will also cause
other monitors to not function as app_server still isn't
multi-head aware (#10486)
