intel driver: added panelfitter pgmming.
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@ -305,7 +305,8 @@ struct intel_shared_info {
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enum pipe_index {
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INTEL_PIPE_ANY,
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INTEL_PIPE_A,
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INTEL_PIPE_B
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INTEL_PIPE_B,
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INTEL_PIPE_C
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};
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//----------------- ioctl() interface ----------------
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@ -1064,6 +1065,7 @@ struct intel_free_graphics_memory {
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#define PCH_PANEL_FITTER_WINDOW_POS 0x70
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#define PCH_PANEL_FITTER_WINDOW_SIZE 0x74
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#define PCH_PANEL_FITTER_CONTROL 0x80
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//not on IvyBridge:
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#define PCH_PANEL_FITTER_V_SCALE 0x84
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#define PCH_PANEL_FITTER_H_SCALE 0x90
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@ -1071,17 +1073,10 @@ struct intel_free_graphics_memory {
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#define PANEL_FITTER_PIPE_MASK (3 << 29)
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#define PANEL_FITTER_PIPE_A (0 << 29)
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#define PANEL_FITTER_PIPE_B (1 << 29)
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#define PANEL_FITTER_PIPE_C (2 << 29)
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#define PANEL_FITTER_SCALING_MODE_MASK (7 << 26)
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#define PANEL_FITTER_FILTER_MASK (3 << 24)
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// panel fitters again, more directly
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#define INTEL_PANELFITTER_0_CTRL (0x8080 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_PANELFITTER_1_CTRL (0x8880 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_PANELFITTER_2_CTRL (0x9080 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_PANELFITTER_0_WINDOW_SIZE (0x8074 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_PANELFITTER_1_WINDOW_SIZE (0x8874 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_PANELFITTER_2_WINDOW_SIZE (0x9074 | REGS_NORTH_PIPE_AND_PORT)
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struct overlay_scale {
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uint32 _reserved0 : 3;
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uint32 horizontal_scale_fraction : 12;
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@ -18,7 +18,7 @@ Addon intel_extreme.accelerant :
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pll.cpp
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# classes
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FlexibleDisplayInterface.cpp
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# PanelFitter.cpp
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PanelFitter.cpp
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Ports.cpp
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Pipes.cpp
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: be $(TARGET_LIBSTDC++) libaccelerantscommon.a
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@ -9,11 +9,12 @@
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#include "PanelFitter.h"
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#include "accelerant.h"
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#include "intel_extreme.h"
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#include <stdlib.h>
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#include <string.h>
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#include <Debug.h>
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#include "accelerant.h"
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#include "intel_extreme.h"
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#undef TRACE
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@ -31,10 +32,20 @@
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// #pragma mark - PanelFitter
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PanelFitter::PanelFitter(int32 pipeIndex)
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PanelFitter::PanelFitter(pipe_index pipeIndex)
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:
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fBaseRegister(PCH_PANEL_FITTER_BASE_REGISTER
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+ pipeIndex * PCH_PANEL_FITTER_PIPE_OFFSET)
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fRegisterBase(PCH_PANEL_FITTER_BASE_REGISTER)
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{
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if (pipeIndex == INTEL_PIPE_B) {
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fRegisterBase += PCH_PANEL_FITTER_PIPE_OFFSET;
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}
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if (pipeIndex == INTEL_PIPE_C) {
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fRegisterBase += 2 * PCH_PANEL_FITTER_PIPE_OFFSET;
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}
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}
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PanelFitter::~PanelFitter()
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{
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}
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@ -42,7 +53,7 @@ PanelFitter::PanelFitter(int32 pipeIndex)
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bool
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PanelFitter::IsEnabled()
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{
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return (read32(fBaseRegister + PCH_PANEL_FITTER_CONTROL)
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return (read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL)
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& PANEL_FITTER_ENABLED) != 0;
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}
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@ -50,8 +61,15 @@ PanelFitter::IsEnabled()
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void
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PanelFitter::Enable(const display_mode& mode)
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{
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// TODO: program the right window size and position based on the mode
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_Enable(true);
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// TODO: program the window position based on the mode, setup/select filter
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// Note: for now assuming fitter was setup by BIOS and pipeA has fitterA, etc.
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TRACE("%s: PCH_PANEL_FITTER_CONTROL, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL));
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TRACE("%s: PCH_PANEL_FITTER_WINDOW_POS, 0x%" B_PRIx32 "\n", __func__, read32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_POS));
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// Window size _must_ be the last register programmed as it 'arms'/unlocks all the other ones..
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write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, (mode.timing.h_display << 16) | mode.timing.v_display);
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}
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@ -59,14 +77,17 @@ void
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PanelFitter::Disable()
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{
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_Enable(false);
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// Window size _must_ be the last register programmed as it 'arms'/unlocks all the other ones..
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write32(fRegisterBase + PCH_PANEL_FITTER_WINDOW_SIZE, 0);
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}
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void
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PanelFitter::_Enable(bool enable)
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{
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uint32 targetRegister = fBaseRegister + PCH_PANEL_FITTER_CONTROL;
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write32(targetRegister, read32(targetRegister) & ~PANEL_FITTER_ENABLED
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uint32 targetRegister = fRegisterBase + PCH_PANEL_FITTER_CONTROL;
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write32(targetRegister, (read32(targetRegister) & ~PANEL_FITTER_ENABLED)
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| (enable ? PANEL_FITTER_ENABLED : 0));
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read32(targetRegister);
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}
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@ -9,9 +9,11 @@
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#define INTEL_FITTER_H
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#include "intel_extreme.h"
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class PanelFitter {
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public:
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PanelFitter(int32 pipeIndex);
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PanelFitter(pipe_index pipeIndex);
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virtual ~PanelFitter();
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bool IsEnabled();
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@ -54,7 +54,7 @@ Pipe::Pipe(pipe_index pipeIndex)
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:
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fHasTranscoder(false),
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fFDILink(NULL),
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// fPanelFitter(NULL),
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fPanelFitter(NULL),
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fPipeIndex(pipeIndex),
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fPipeOffset(0),
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fPlaneOffset(0)
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@ -75,6 +75,8 @@ Pipe::Pipe(pipe_index pipeIndex)
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// Program FDILink if PCH
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fFDILink = new(std::nothrow) FDILink(pipeIndex);
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// Program gen5(+) style panelfitter as well
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fPanelFitter = new(std::nothrow) PanelFitter(pipeIndex);
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}
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TRACE("Pipe %s. Pipe Base: 0x%" B_PRIxADDR
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@ -16,6 +16,7 @@
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#include "pll.h"
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#include "FlexibleDisplayInterface.h"
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#include "PanelFitter.h"
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#define MAX_PIPES 2
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@ -49,8 +50,8 @@ public:
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// access to the various parts of the pipe
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::FDILink* FDI()
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{ return fFDILink; }
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// ::PanelFitter* PanelFitter()
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// { return fPanelFitter; }
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::PanelFitter* PFT()
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{ return fPanelFitter; }
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private:
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void _ConfigureTranscoder(display_mode* mode);
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@ -58,7 +59,7 @@ private:
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bool fHasTranscoder;
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FDILink* fFDILink;
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// PanelFitter* fPanelFitter;
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PanelFitter* fPanelFitter;
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pipe_index fPipeIndex;
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@ -316,12 +316,12 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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}
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// Setup PanelFitter and Train FDI if it exists
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PanelFitter* fitter = fPipe->PFT();
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if (fitter != NULL)
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fitter->Enable(*target);
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FDILink* link = fPipe->FDI();
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if (link != NULL) {
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// fixme insert fitter setup here
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if (link != NULL)
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link->Train(target);
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}
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pll_divisors divisors;
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compute_pll_divisors(target, &divisors, false);
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@ -501,12 +501,12 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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}
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// Setup PanelFitter and Train FDI if it exists
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PanelFitter* fitter = fPipe->PFT();
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if (fitter != NULL)
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fitter->Enable(*target);
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FDILink* link = fPipe->FDI();
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if (link != NULL) {
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// fixme insert fitter setup here
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if (link != NULL)
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link->Train(target);
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}
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// For LVDS panels, we may need to set the timings according to the panel
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// native video mode, and let the panel fitter do the scaling. But the
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@ -736,12 +736,12 @@ DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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}
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// Setup PanelFitter and Train FDI if it exists
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PanelFitter* fitter = fPipe->PFT();
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if (fitter != NULL)
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fitter->Enable(*target);
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FDILink* link = fPipe->FDI();
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if (link != NULL) {
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// fixme insert fitter setup here
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if (link != NULL)
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link->Train(target);
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}
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pll_divisors divisors;
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compute_pll_divisors(target, &divisors, false);
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