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intel_extreme: Rework PLL and id PineView as PIN

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This commit is contained in:
Alexander von Gluck IV 2015-12-04 13:18:38 -06:00
parent 77b8386d56
commit 3cfe299798
7 changed files with 55 additions and 22 deletions
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8
headers/private/graphics/intel_extreme/intel_extreme.h
View File

@ -40,7 +40,7 @@
#define INTEL_GROUP_96x (INTEL_FAMILY_9xx | 0x0040)
#define INTEL_GROUP_Gxx (INTEL_FAMILY_9xx | 0x0080)
#define INTEL_GROUP_G4x (INTEL_FAMILY_9xx | 0x0100)
#define INTEL_GROUP_IGD (INTEL_FAMILY_9xx | 0x0200)
#define INTEL_GROUP_PIN (INTEL_FAMILY_9xx | 0x0200) // PineView
#define INTEL_GROUP_ILK (INTEL_FAMILY_SER5 | 0x0010) // IronLake
#define INTEL_GROUP_SNB (INTEL_FAMILY_SER5 | 0x0020) // SandyBridge
#define INTEL_GROUP_IVB (INTEL_FAMILY_SER5 | 0x0040) // IvyBridge
@ -62,8 +62,8 @@
#define INTEL_MODEL_G33 (INTEL_GROUP_Gxx)
#define INTEL_MODEL_G45 (INTEL_GROUP_G4x)
#define INTEL_MODEL_GM45 (INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_IGDG (INTEL_GROUP_IGD)
#define INTEL_MODEL_IGDGM (INTEL_GROUP_IGD | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_PINE (INTEL_GROUP_PIN)
#define INTEL_MODEL_PINEM (INTEL_GROUP_PIN | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_ILKG (INTEL_GROUP_ILK)
#define INTEL_MODEL_ILKGM (INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_SNBG (INTEL_GROUP_SNB)
@ -169,7 +169,7 @@ struct DeviceType {
if (InFamily(INTEL_FAMILY_8xx))
return 2;
if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
|| IsModel(INTEL_MODEL_G33))
|| IsModel(INTEL_MODEL_G33) || InGroup(INTEL_GROUP_PIN))
return 3;
if (InFamily(INTEL_FAMILY_9xx))
return 4;

14
src/add-ons/accelerants/intel_extreme/Pipes.cpp
View File

@ -187,7 +187,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
// XXX: For now we assume no LVDS downclocking and program the same divisor
// value to both divisor 0 (standard) and 1 (reduced divisor)
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
write32(pllDivisorA, (((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
@ -213,8 +213,10 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags;
if (gInfo->shared_info->device_type.Generation() >= 4) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
if (gInfo->shared_info->device_type.Generation() >= 4
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
pll |= ((1 << (divisors.post1 - 1))
<< DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_IGD_POST1_DIVISOR_MASK;
@ -222,9 +224,10 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
pll |= ((1 << (divisors.post1 - 1))
<< DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
// pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
// pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
}
#if 0
// TODO: ??? LVDS?
switch (divisors.post2) {
@ -234,6 +237,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock,
break;
}
#endif
if (divisors.post2_high)
pll |= DISPLAY_PLL_DIVIDE_HIGH;

2
src/add-ons/accelerants/intel_extreme/hooks.cpp
View File

@ -115,7 +115,7 @@ get_accelerant_hook(uint32 feature, void* data)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
|| gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965M)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_G4x)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_POVR)

4
src/add-ons/accelerants/intel_extreme/mode.cpp
View File

@ -78,7 +78,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
}
pll_divisors divisors;
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
divisors.m1 = 0;
divisors.m2 = (pllDivisor & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)
>> DISPLAY_PLL_M2_DIVISOR_SHIFT;
@ -100,7 +100,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
divisors.post1 = (pll & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK)
>> DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT;
} else {

39
src/add-ons/accelerants/intel_extreme/pll.cpp
View File

@ -79,7 +79,7 @@ get_pll_limits(pll_limits* limits, bool isLVDS)
270000, 1750000, 3500000
};
memcpy(limits, &kLimits, sizeof(pll_limits));
} else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
} else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
// TODO: support LVDS output limits as well
// m1 is reserved and must be 0
pll_limits kLimits = {
@ -130,6 +130,35 @@ valid_pll_divisors(pll_divisors* divisors, pll_limits* limits)
}
static uint32
compute_pll_m(pll_divisors* divisors)
{
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV)
|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV)) {
return divisors->m1 * divisors->m2;
}
// Pineview, m1 is reserved
if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN))
return divisors->m2 + 2;
if (gInfo->shared_info->device_type.Generation() >= 3)
return 5 * (divisors->m1 + 2) + (divisors->m2 + 2);
// TODO: This logic needs validated... PLL's were calculated differently
// on 8xx chipsets
return 5 * divisors->m1 + divisors->m2;
}
static uint32
compute_pll_p(pll_divisors* divisors)
{
return divisors->post1 * divisors->post2;
}
void
compute_pll_divisors(display_mode* current, pll_divisors* divisors,
bool isLVDS)
@ -164,17 +193,17 @@ compute_pll_divisors(display_mode* current, pll_divisors* divisors,
float best = requestedPixelClock;
pll_divisors bestDivisors;
bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD);
bool is_pine = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN);
for (divisors->m1 = limits.min.m1; divisors->m1 <= limits.max.m1;
divisors->m1++) {
for (divisors->m2 = limits.min.m2; divisors->m2 <= limits.max.m2
&& ((divisors->m2 < divisors->m1) || is_igd); divisors->m2++) {
&& ((divisors->m2 < divisors->m1) || is_pine); divisors->m2++) {
for (divisors->n = limits.min.n; divisors->n <= limits.max.n;
divisors->n++) {
for (divisors->post1 = limits.min.post1;
divisors->post1 <= limits.max.post1; divisors->post1++) {
divisors->m = 5 * divisors->m1 + divisors->m2;
divisors->post = divisors->post1 * divisors->post2;
divisors->m = compute_pll_m(divisors);
divisors->post = compute_pll_p(divisors);
if (!valid_pll_divisors(divisors, &limits))
continue;

6
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
View File

@ -90,8 +90,8 @@ const struct supported_device {
{0x2e40, 0x2e42, INTEL_MODEL_G45, "B43"},
{0x2e90, 0x2e92, INTEL_MODEL_G45, "B43"},
{0xa000, 0xa001, INTEL_MODEL_IGDG, "Atom_Dx10"},
{0xa010, 0xa011, INTEL_MODEL_IGDGM, "Atom_N4x0"},
{0xa000, 0xa001, INTEL_MODEL_PINE, "Atom_Dx10"},
{0xa010, 0xa011, INTEL_MODEL_PINEM, "Atom_N4x0"},
{0x0040, 0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"},
{0x0044, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
@ -327,7 +327,7 @@ determine_gtt_size(intel_info &info)
break;
}
} else if (info.type->IsModel(INTEL_MODEL_G33)
|| info.type->InGroup(INTEL_GROUP_IGD)) {
|| info.type->InGroup(INTEL_GROUP_PIN)) {
switch (memoryConfig & G33_GTT_MASK) {
case G33_GTT_1M:
gttSize = 1 << 20;

4
src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
View File

@ -74,8 +74,8 @@ const struct supported_device {
{0x2e42, INTEL_MODEL_G45, "B43"},
{0x2e92, INTEL_MODEL_G45, "B43"},
{0xa001, INTEL_MODEL_IGDG, "Atom_Dx10"},
{0xa011, INTEL_MODEL_IGDGM, "Atom_N4x0"},
{0xa001, INTEL_MODEL_PINE, "Atom_Dx10"},
{0xa011, INTEL_MODEL_PINEM, "Atom_N4x0"},
{0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"},
{0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},