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intel_extreme: Add general pipe configuration and adjust color space

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This commit is contained in:
Alexander von Gluck IV 2016-02-19 00:09:43 -06:00
parent 6eae8422d1
commit c9c61669ea
4 changed files with 58 additions and 0 deletions
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14
headers/private/graphics/intel_extreme/intel_extreme.h
View File

@ -585,6 +585,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL)
// i965 and up only
// INTEL_DISPLAY_A_CONTROL source pixel format
#define DISPLAY_CONTROL_ENABLED (1UL << 31)
#define DISPLAY_CONTROL_GAMMA (1UL << 30)
#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
@ -593,6 +594,19 @@ struct intel_free_graphics_memory {
#define DISPLAY_CONTROL_RGB16 (5UL << 26)
#define DISPLAY_CONTROL_RGB32 (6UL << 26)
// INTEL_DISPLAY_A_PIPE_CONTROL ILK+
#define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c)
#define INTEL_PIPE_DITHER_TYPE_SP (0 << 2)
#define INTEL_PIPE_DITHER_TYPE_ST1 (1 << 2)
#define INTEL_PIPE_DITHER_TYPE_ST2 (2 << 2)
#define INTEL_PIPE_DITHER_TYPE_TEMP (3 << 2)
#define INTEL_PIPE_DITHER_EN (1 << 4)
#define INTEL_PIPE_8BPC (0 << 5)
#define INTEL_PIPE_10BPC (1 << 5)
#define INTEL_PIPE_6BPC (2 << 5)
#define INTEL_PIPE_12BPC (3 << 5)
#define INTEL_PIPE_PROGRESSIVE (0 << 21)
// cursors
#define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL)

34
src/add-ons/accelerants/intel_extreme/Pipes.cpp
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@ -93,6 +93,40 @@ Pipe::IsEnabled()
}
void
Pipe::Configure(display_mode* mode)
{
uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
// TODO: Haswell+ dithering changes.
if (gInfo->shared_info->device_type.Generation() >= 4) {
pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP);
switch (mode->space) {
case B_CMAP8:
case B_RGB15_LITTLE:
case B_RGB16_LITTLE:
pipeControl |= INTEL_PIPE_6BPC;
break;
case B_RGB24_LITTLE:
pipeControl |= INTEL_PIPE_8BPC;
break;
case B_RGB32_LITTLE:
default:
pipeControl |= INTEL_PIPE_10BPC;
break;
}
}
// TODO: CxSR downclocking?
// TODO: Interlaced modes
pipeControl |= INTEL_PIPE_PROGRESSIVE;
write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl);
read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset);
}
void
Pipe::_ConfigureTranscoder(display_mode* target)
{

1
src/add-ons/accelerants/intel_extreme/Pipes.h
View File

@ -38,6 +38,7 @@ public:
void Enable(bool enable);
void Disable();
void Configure(display_mode* mode);
void ConfigureTimings(display_mode* mode);
void ConfigureClocks(
const pll_divisors& divisors,

9
src/add-ons/accelerants/intel_extreme/Ports.cpp
View File

@ -314,6 +314,9 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
if (gInfo->shared_info->device_type.Generation() >= 3)
extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
// Program general pipe config
fPipe->Configure(target);
// Program pipe PLL's
fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
@ -567,6 +570,9 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
if (gInfo->shared_info->device_type.Generation() >= 3)
extraPLLFlags |= DISPLAY_PLL_MODE_LVDS;
// Program general pipe config
fPipe->Configure(target);
// Program pipe PLL's (pixel_clock is *always* the hardware pixel clock)
fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
@ -745,6 +751,9 @@ DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
if (gInfo->shared_info->device_type.Generation() >= 3)
extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
// Program general pipe config
fPipe->Configure(target);
// Program pipe PLL's
fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);