intel_extreme: Intial work for ValleyView support
* No impact to non-ValleyView chipsets * Bump some register locations for VLV * Only have HDMI port to test with on my ValleyView GPU and our driver seems to be missing all HDMI and sideband functionality. * As ValleyView chipsets seem to be UEFI only, we don't have VESA fallback, so this shouldn't cause regressions. (unless we get UEFI framebuffer support)
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@ -39,6 +39,7 @@
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#define INTEL_TYPE_ILK (INTEL_TYPE_9xx | 0x1000)
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#define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x2000)
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#define INTEL_TYPE_IVB (INTEL_TYPE_9xx | 0x4000)
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#define INTEL_TYPE_VLV (INTEL_TYPE_9xx | 0x8000)
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// models
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#define INTEL_TYPE_SERVER 0x0004
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#define INTEL_TYPE_MOBILE 0x0008
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@ -61,6 +62,11 @@
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#define INTEL_TYPE_IVBG (INTEL_TYPE_IVB)
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#define INTEL_TYPE_IVBGM (INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
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#define INTEL_TYPE_IVBGS (INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
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#define INTEL_TYPE_VLVG (INTEL_TYPE_VLV)
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#define INTEL_TYPE_VLVGM (INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
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// ValleyView MMIO offset
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#define VLV_DISPLAY_BASE 0x180000
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#define DEVICE_NAME "intel_extreme"
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#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
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@ -131,7 +137,7 @@ struct DeviceType {
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bool HasPlatformControlHub() const
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{
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return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
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|| InGroup(INTEL_TYPE_IVB);
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|| InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_VLV);
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}
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};
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@ -166,6 +172,7 @@ struct intel_shared_info {
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area_id registers_area; // area of memory mapped registers
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uint32 register_blocks[REGISTER_BLOCK_COUNT];
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uint8* status_page;
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phys_addr_t physical_status_page;
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uint8* graphics_memory;
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@ -368,7 +375,6 @@ struct intel_free_graphics_memory {
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#define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
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// display ports
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#define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT)
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#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
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#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
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#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
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@ -380,9 +386,6 @@ struct intel_free_graphics_memory {
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#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
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#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
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#define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_C_DIGITAL (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT)
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#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
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#define LVDS_POST2_RATE_FAST 7
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#define LVDS_CLKB_POWER_MASK (3 << 4)
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@ -436,7 +439,11 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_C_DIGITAL (0x1160 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_LVDS_PORT (0x1180 | REGS_SOUTH_TRANSCODER_PORT)
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// planes
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#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
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@ -118,7 +118,8 @@ get_accelerant_hook(uint32 feature, void* data)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB))
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV))
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return NULL;
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return (void*)intel_allocate_overlay_buffer;
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@ -140,7 +140,8 @@ get_pll_limits(pll_limits &limits)
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)) {
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
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|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV)) {
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// TODO: support LVDS output limits as well
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static const pll_limits kLimits = {
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// p, p1, p2, high, n, m, m1, m2
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@ -351,6 +352,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
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controlRegister = INTEL_DISPLAY_B_CONTROL;
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} else {
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// TODO: not supported
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TRACE("%s: pllRegister not yet supported\n", __func__);
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return;
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}
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@ -565,7 +567,8 @@ set_frame_buffer_base()
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_ILK)
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)) {
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_VLV)) {
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write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
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+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
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read32(baseRegister);
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@ -1,6 +1,14 @@
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/*
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* Copyright 2008-2010, Axel Dörfler, axeld@pinc-software.de.
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* Copyright 2011-2015, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Jerome Duval, jerome.duval@gmail.com
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* Adrien Destugues, pulkomandy@gmail.com
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* Michael Lotz, mmlr@mlotz.ch
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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@ -104,6 +112,14 @@ const struct supported_device {
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{0x0c00, 0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
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{0x0c04, 0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
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{0x0d04, 0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
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// XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31
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{0x0f00, 0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
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{0x0f00, 0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f00, 0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f00, 0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f00, 0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f00, 0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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};
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struct intel_info {
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@ -392,6 +408,7 @@ intel_map(intel_info &info)
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info.display.u.h0.base_registers[mmioIndex],
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info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers);
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if (mmioMapper.InitCheck() < B_OK) {
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dprintf("agp_intel: could not map memory I/O!\n");
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return info.registers_area;
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@ -100,6 +100,13 @@ const struct supported_device {
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{0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
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{0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
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{0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
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{0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
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{0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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{0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
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};
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int32 api_version = B_CUR_DRIVER_API_VERSION;
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@ -4,6 +4,7 @@
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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= ICH_PORT_REGISTER_BASE;
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}
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// "I nearly got violent with the hw guys when they told me..."
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if (info.device_type.InFamily(INTEL_TYPE_VLV)) {
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TRACE("%s: ValleyView MMIO offset engaged\n", __func__);
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blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
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blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] += VLV_DISPLAY_BASE;
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blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
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}
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// make sure bus master, memory-mapped I/O, and frame buffer is enabled
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set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci,
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PCI_command, 2) | PCI_command_io | PCI_command_memory
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@ -37,6 +37,9 @@ intel_en_gating(intel_info &info)
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} else if (info.device_type.InGroup(INTEL_TYPE_IVB)) {
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TRACE("IvyBridge clock gating\n");
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write32(info, 0x42020, (1L << 28));
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} else if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
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TRACE("ValleyView clock gating\n");
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write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));
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} else if (info.device_type.InGroup(INTEL_TYPE_ILK)) {
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TRACE("IronLake clock gating\n");
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write32(info, 0x42020, (1L << 7) | (1L << 5));
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write32(info, INTEL6_PMINTRMSK, 0);
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return B_OK;
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}
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}
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