intel_extreme: don't pgm pipes, follow BIOS for now. Two screens on now i.e.

headers/private/graphics/intel_extreme/intel_extreme.h

@@ -474,7 +474,7 @@ struct intel_free_graphics_memory {
 #define PCH_INTERRUPT_VBLANK_PIPEB_SNB		(1 << 15)
 #define PCH_INTERRUPT_GLOBAL_SNB			(1 << 31)
 
-// graphics port control
+// graphics port control (i.e. G45)
 #define DISPLAY_MONITOR_PORT_ENABLED	(1UL << 31)
 #define DISPLAY_MONITOR_PIPE_B			(1UL << 30)
 #define DISPLAY_MONITOR_VGA_POLARITY	(1UL << 15)
@@ -643,6 +643,14 @@ struct intel_free_graphics_memory {
 #define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_SOUTH_TRANSCODER_PORT)
 #define INTEL_DISPLAY_PORT_D			(0x4300 | REGS_SOUTH_TRANSCODER_PORT)
 
+#define INTEL_TRANSCODER_A_DP_CTL		(0x0300 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_TRANSCODER_B_DP_CTL		(0x1300 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_TRANSCODER_C_DP_CTL		(0x2300 | REGS_SOUTH_TRANSCODER_PORT)
+
+#define INTEL_TRANS_DP_COLOR_SHIFT		9
+#define INTEL_TRANS_DP_BPC(x)			((x) << INTEL_PIPE_COLOR_SHIFT)
+#define INTEL_TRANS_DP_BPC_MASK			(7 << INTEL_PIPE_COLOR_SHIFT)
+
 // Unless you're a damn Valley/CherryView unicorn :-(
 #define VLV_DISPLAY_PORT_B				(VLV_DISPLAY_BASE + 0x64100)
 #define VLV_DISPLAY_PORT_C				(VLV_DISPLAY_BASE + 0x64200)

src/add-ons/accelerants/intel_extreme/Pipes.cpp

@@ -406,7 +406,12 @@ Pipe::Enable(bool enable)
 		write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED);
 
 		//Enable default display main watermarks
-		write32(INTEL_DISPLAY_A_PIPE_WATERMARK, 0x0783818);
+		if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
+			if (fPipeOffset == 0)
+				write32(INTEL_DISPLAY_A_PIPE_WATERMARK, 0x0783818);
+			else
+				write32(INTEL_DISPLAY_B_PIPE_WATERMARK, 0x0783818);
+		}
 	} else {
 		write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED);
 		wait_for_vblank();

src/add-ons/accelerants/intel_extreme/Ports.cpp

@@ -134,7 +134,7 @@ Port::SetPipe(Pipe* pipe)
 	// FIXME is the use of PORT_TRANS_* constants correct for Sandy Bridge /
 	// Cougar Point? Or is it only for Ivy Bridge / Panther point onwards?
 	if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
-		portState &= ~PORT_TRANS_SEL_MASK; //fixme should be done sooner, not here!
+		portState &= ~PORT_TRANS_SEL_MASK;
 		if (pipe->Index() == INTEL_PIPE_A)
 			write32(portRegister, portState | PORT_TRANS_A_SEL_CPT);
 		else
@@ -224,6 +224,40 @@ Port::GetPLLLimits(pll_limits& limits)
 }
 
 
+pipe_index
+Port::PipePreference()
+{
+	// Ideally we could just return INTEL_PIPE_ANY for all devices by default, but
+	// this doesn't quite work yet. We need to use the BIOS presetup pipes for now.
+	if (gInfo->shared_info->device_type.Generation() < 4)
+		return INTEL_PIPE_ANY;
+
+	// Notes:
+	// - The BIOSes seen sofar do not use PIPE C by default.
+	// - The BIOSes seen sofar program transcoder A to PIPE A, etc.
+	// - Later devices add a pipe C alongside the added transcoder C.
+
+	// FIXME How's this setup in newer gens? Currently return INTEL_PIPE_ANY there..
+	if (gInfo->shared_info->device_type.Generation() <= 7) {
+		uint32 portState = read32(_PortRegister());
+		if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
+			portState &= PORT_TRANS_SEL_MASK;
+			if (portState == PORT_TRANS_B_SEL_CPT)
+				return INTEL_PIPE_B;
+			else
+				return INTEL_PIPE_A;
+		} else {
+			if (portState & DISPLAY_MONITOR_PIPE_B)
+				return INTEL_PIPE_B;
+			else
+				return INTEL_PIPE_A;
+		}
+	}
+
+	return INTEL_PIPE_ANY;
+}
+
+
 status_t
 Port::_GetI2CSignals(void* cookie, int* _clock, int* _data)
 {
@@ -386,22 +420,34 @@ LVDSPort::PipePreference()
 	// Ideally we could just return INTEL_PIPE_ANY for the newer devices, but
 	// this doesn't quite work yet.
 
-	// For Ibex Point and SandyBridge, read the existing LVDS configuration and
-	// just reuse that (it seems our attempt to change it doesn't work, anyway)
-	// On SandyBridge, there is a transcoder C that can't be used by the LVDS
-	// port (but A and B would be fine).
-	if (gInfo->shared_info->device_type.Generation() <= 6) {
+	// On SandyBridge and later, there is a transcoder C. On SandyBridge at least
+	// that can't be used by the LVDS port (but A and B would be fine).
+	// On Ibex Point, SandyBridge and IvyBridge (tested) changing pipes does not
+	// work yet.
+	// Notes:
+	// - Switching Pipes only works reliably when a 'full modeswitch' is executed
+	//   (FDI training) so we have to reuse the BIOS preset setup always for now.
+	// - The BIOSes seen sofar do not use PIPE C by default.
+	// - The BIOSes seen sofar program transcoder A to PIPE A, etc.
+	// - Later devices add a pipe C alongside the added transcoder C.
+
+	// FIXME How's this setup in newer gens? Currently return Pipe B fixed there..
+	if (gInfo->shared_info->device_type.Generation() <= 7) {
 		uint32 portState = read32(_PortRegister());
-		if (portState & DISPLAY_MONITOR_PIPE_B)
-			return INTEL_PIPE_B;
-		else
-			return INTEL_PIPE_A;
+		if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
+			portState &= PORT_TRANS_SEL_MASK;
+			if (portState == PORT_TRANS_B_SEL_CPT)
+				return INTEL_PIPE_B;
+			else
+				return INTEL_PIPE_A;
+		} else {
+			if (portState & DISPLAY_MONITOR_PIPE_B)
+				return INTEL_PIPE_B;
+			else
+				return INTEL_PIPE_A;
+		}
 	}
 
-	// For later generations, assume pipe B for now. Note that later devices
-	// add a pipe C (and a transcoder C), so we'd need to handle that and the
-	// port register has a different format because of it.
-	// (using PORT_TRANS_*_SEL_CPT to select which transcoder to use)
 	return INTEL_PIPE_B;
 }
 

src/add-ons/accelerants/intel_extreme/Ports.h

@@ -72,8 +72,8 @@ virtual	status_t					GetPLLLimits(pll_limits& limits);
 virtual status_t					SetDisplayMode(display_mode* mode,
 										uint32 colorMode) { return B_ERROR; };
 
-virtual pipe_index					PipePreference()
-										{ return INTEL_PIPE_ANY; };
+virtual pipe_index					PipePreference();
+//										{ return INTEL_PIPE_ANY; };
 
 protected:
 		void						_SetName(const char* name);