intel_extreme: Fix i965 LVDS panel programming
* polarity regs move on LVDS vs analog * add knowledge or transcoder registers, they exist seperately on PCH-split * Native resolutions now work on LVDS under i965
This commit is contained in:
Alexander von Gluck IV
parent
e28962a280
commit
d35a52e8e2
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@ -448,18 +448,18 @@ struct intel_free_graphics_memory {
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#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
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#define LVDS_POST2_RATE_FAST 7
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#define LVDS_B0B3_POWER_MASK (3 << 2)
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#define LVDS_B0B3_POWER_UP (3 << 2)
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#define LVDS_CLKB_POWER_MASK (3 << 4)
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#define LVDS_CLKB_POWER_UP (3 << 4)
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#define LVDS_A3_POWER_MASK (3 << 6)
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#define LVDS_A3_POWER_UP (3 << 6)
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#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
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#define LVDS_BORDER_ENABLE (1 << 15)
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#define LVDS_HSYNC_POLARITY (1 << 20)
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#define LVDS_VSYNC_POLARITY (1 << 21)
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#define LVDS_18BIT_DITHER (1 << 25)
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#define LVDS_PORT_EN (1 << 31)
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#define LVDS_B0B3_POWER_MASK (3UL << 2)
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#define LVDS_B0B3_POWER_UP (3UL << 2)
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#define LVDS_CLKB_POWER_MASK (3UL << 4)
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#define LVDS_CLKB_POWER_UP (3UL << 4)
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#define LVDS_A3_POWER_MASK (3UL << 6)
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#define LVDS_A3_POWER_UP (3UL << 6)
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#define LVDS_A0A2_CLKA_POWER_UP (3UL << 8)
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#define LVDS_BORDER_ENABLE (1UL << 15)
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#define LVDS_HSYNC_POLARITY (1UL << 20)
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#define LVDS_VSYNC_POLARITY (1UL << 21)
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#define LVDS_18BIT_DITHER (1UL << 25)
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#define LVDS_PORT_EN (1UL << 31)
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// PLL flags
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@ -508,6 +508,23 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
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// on PCH we also have to set the transcoder
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#define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_ANALOG_PORT (0x1100 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DIGITAL_PORT_A (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DIGITAL_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
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@ -52,26 +52,29 @@ program_pipe_color_modes(uint32 colorMode)
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Pipe::Pipe(pipe_index pipeIndex)
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:
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fHasTranscoder(false),
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fFDILink(NULL),
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// fPanelFitter(NULL),
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fPipeIndex(pipeIndex),
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fPipeBase(REGS_NORTH_PIPE_AND_PORT),
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fPlaneBase(REGS_NORTH_PLANE_CONTROL)
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fPipeOffset(0),
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fPlaneOffset(0)
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{
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if (pipeIndex == INTEL_PIPE_B) {
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fPipeBase += INTEL_DISPLAY_OFFSET;
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fPlaneBase += INTEL_PLANE_OFFSET;
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fPipeOffset = INTEL_DISPLAY_OFFSET;
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fPlaneOffset = INTEL_PLANE_OFFSET;
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}
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// Program FDILink if PCH
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if (gInfo->shared_info->device_type.HasPlatformControlHub()) {
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fHasTranscoder = true;
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// Program FDILink if PCH
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if (fFDILink == NULL)
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fFDILink = new(std::nothrow) FDILink(pipeIndex);
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}
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TRACE("Pipe %s. Pipe Base: 0x%" B_PRIxADDR
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" Plane Base: 0x% " B_PRIxADDR "\n", (pipeIndex == INTEL_PIPE_A)
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? "A" : "B", fPipeBase, fPlaneBase);
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? "A" : "B", fPipeOffset, fPlaneOffset);
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}
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@ -84,12 +87,47 @@ bool
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Pipe::IsEnabled()
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{
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CALLED();
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return (read32(fPlaneBase + INTEL_PIPE_CONTROL) & INTEL_PIPE_ENABLED) != 0;
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return (read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPlaneOffset)
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& INTEL_PIPE_ENABLED) != 0;
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}
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void
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Pipe::Enable(display_mode* target, addr_t portAddress)
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Pipe::_EnableTranscoder(display_mode* target)
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{
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// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
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write32(INTEL_TRANSCODER_A_HTOTAL + fPipeOffset,
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((uint32)(target->timing.h_total - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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write32(INTEL_TRANSCODER_A_HBLANK + fPipeOffset,
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((uint32)(target->timing.h_total - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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write32(INTEL_TRANSCODER_A_HSYNC + fPipeOffset,
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((uint32)(target->timing.h_sync_end - 1) << 16)
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| ((uint32)target->timing.h_sync_start - 1));
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write32(INTEL_TRANSCODER_A_VTOTAL + fPipeOffset,
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((uint32)(target->timing.v_total - 1) << 16)
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| ((uint32)target->timing.v_display - 1));
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write32(INTEL_TRANSCODER_A_VBLANK + fPipeOffset,
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((uint32)(target->timing.v_total - 1) << 16)
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| ((uint32)target->timing.v_display - 1));
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write32(INTEL_TRANSCODER_A_VSYNC + fPipeOffset,
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((uint32)(target->timing.v_sync_end - 1) << 16)
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| ((uint32)target->timing.v_sync_start - 1));
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#if 0
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// XXX: Is it ok to do these on non-digital?
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write32(INTEL_TRANSCODER_A_POS + fPipeOffset, 0);
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write32(INTEL_TRANSCODER_A_IMAGE_SIZE + fPipeOffset,
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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#endif
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}
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void
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Pipe::Enable(display_mode* target)
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{
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CALLED();
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@ -97,58 +135,48 @@ Pipe::Enable(display_mode* target, addr_t portAddress)
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ERROR("%s: Invalid display mode!\n", __func__);
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return;
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}
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if (portAddress == 0) {
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ERROR("%s: Invalid port address!\n", __func__);
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return;
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}
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// update timing (fPipeBase bumps the DISPLAY_A to B when needed)
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HTOTAL),
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// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
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write32(INTEL_DISPLAY_A_HTOTAL + fPipeOffset,
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((uint32)(target->timing.h_total - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HBLANK),
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write32(INTEL_DISPLAY_A_HBLANK + fPipeOffset,
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((uint32)(target->timing.h_total - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HSYNC),
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write32(INTEL_DISPLAY_A_HSYNC + fPipeOffset,
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((uint32)(target->timing.h_sync_end - 1) << 16)
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| ((uint32)target->timing.h_sync_start - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_VTOTAL),
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write32(INTEL_DISPLAY_A_VTOTAL + fPipeOffset,
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((uint32)(target->timing.v_total - 1) << 16)
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| ((uint32)target->timing.v_display - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_VBLANK),
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write32(INTEL_DISPLAY_A_VBLANK + fPipeOffset,
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((uint32)(target->timing.v_total - 1) << 16)
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| ((uint32)target->timing.v_display - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_VSYNC),
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write32(INTEL_DISPLAY_A_VSYNC + fPipeOffset,
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((uint32)(target->timing.v_sync_end - 1) << 16)
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| ((uint32)target->timing.v_sync_start - 1));
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// XXX: Is it ok to do these on non-digital?
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0);
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE),
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write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
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write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset,
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE),
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write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset,
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((uint32)(target->timing.v_display - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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// This is useful for debugging: it sets the border to red, so you
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// can see what is border and what is porch (black area around the
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// sync)
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//write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000);
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//write32(INTEL_DISPLAY_A_RED + fPipeOffset, 0x00FF0000);
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// XXX: Is it ok to do this on non-analog?
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write32(portAddress, (read32(portAddress) & ~(DISPLAY_MONITOR_POLARITY_MASK
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| DISPLAY_MONITOR_VGA_POLARITY))
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| ((target->timing.flags & B_POSITIVE_HSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
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| ((target->timing.flags & B_POSITIVE_VSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_VSYNC : 0));
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if (fHasTranscoder)
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_EnableTranscoder(target);
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// Enable display pipe
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_Enable(true);
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}
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@ -263,7 +291,7 @@ Pipe::_Enable(bool enable)
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{
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CALLED();
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addr_t targetRegister = fPlaneBase + INTEL_PIPE_CONTROL;
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addr_t targetRegister = INTEL_DISPLAY_A_PIPE_CONTROL + fPlaneOffset;
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write32(targetRegister, (read32(targetRegister) & ~INTEL_PIPE_ENABLED)
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| (enable ? INTEL_PIPE_ENABLED : 0));
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@ -35,8 +35,7 @@ public:
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{ return fPipeIndex; }
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bool IsEnabled();
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void Enable(display_mode* mode,
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addr_t portRegister);
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void Enable(display_mode* mode);
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void Disable();
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void ConfigureTimings(
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@ -52,14 +51,17 @@ public:
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private:
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void _Enable(bool enable);
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void _EnableTranscoder(display_mode* mode);
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bool fHasTranscoder;
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FDILink* fFDILink;
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// PanelFitter* fPanelFitter;
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pipe_index fPipeIndex;
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addr_t fPipeBase;
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addr_t fPlaneBase;
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addr_t fPipeOffset;
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addr_t fPlaneOffset;
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};
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@ -305,12 +305,19 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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if (gInfo->shared_info->device_type.Generation() >= 4)
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extraPLLFlags |= DISPLAY_PLL_MODE_NORMAL;
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write32(_PortRegister(), (read32(_PortRegister())
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& ~(DISPLAY_MONITOR_POLARITY_MASK | DISPLAY_MONITOR_VGA_POLARITY))
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| ((target->timing.flags & B_POSITIVE_HSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_HSYNC : 0)
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| ((target->timing.flags & B_POSITIVE_VSYNC) != 0
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? DISPLAY_MONITOR_POSITIVE_VSYNC : 0));
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// Program pipe PLL's
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fPipe->ConfigureTimings(divisors, target->timing.pixel_clock,
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extraPLLFlags);
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// Program target display mode
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fPipe->Enable(target, _PortRegister());
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fPipe->Enable(target);
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// Set fCurrentMode to our set display mode
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memcpy(&fCurrentMode, target, sizeof(display_mode));
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@ -345,7 +352,7 @@ LVDSPort::IsConnected()
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}
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}
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uint32 registerValue = read32(INTEL_DIGITAL_LVDS_PORT);
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uint32 registerValue = read32(_PortRegister());
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if (gInfo->shared_info->device_type.HasPlatformControlHub()) {
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// there's a detection bit we can use
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if ((registerValue & PCH_LVDS_DETECTED) == 0) {
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@ -524,11 +531,15 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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// Set the B0-B3 data pairs corresponding to whether we're going to
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// set the DPLLs for dual-channel mode or not.
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if (divisors.post2_high)
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if (divisors.post2_high) {
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TRACE("LVDS: dual channel\n");
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lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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else
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} else {
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TRACE("LVDS: single channel\n");
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lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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}
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// LVDS port control moves polarity bits because Intel hates you.
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// Set LVDS sync polarity
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lvds &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
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@ -538,7 +549,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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if ((target->timing.flags & B_POSITIVE_VSYNC) == 0)
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lvds |= LVDS_VSYNC_POLARITY;
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TRACE("%s: LVDS Control: 0x%" B_PRIx32 "\n", __func__, lvds);
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TRACE("%s: LVDS Write: 0x%" B_PRIx32 "\n", __func__, lvds);
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write32(_PortRegister(), lvds);
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read32(_PortRegister());
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@ -560,7 +571,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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ERROR("%s: %s didn't power on within 1000ms!\n", __func__, PortName());
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// Program target display mode
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fPipe->Enable(target, _PortRegister());
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fPipe->Enable(target);
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#if 0
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@ -732,7 +743,7 @@ DigitalPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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extraPLLFlags);
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// Program target display mode
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fPipe->Enable(target, _PortRegister());
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fPipe->Enable(target);
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// Set fCurrentMode to our set display mode
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memcpy(&fCurrentMode, target, sizeof(display_mode));
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