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intel_extreme: Add generation index + begin to use in gart

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This commit is contained in:
Alexander von Gluck IV 2015-11-02 15:55:05 -06:00
parent 53f5bffe84
commit e2e5daf25b
2 changed files with 44 additions and 16 deletions
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28
headers/private/graphics/intel_extreme/intel_extreme.h
View File

@ -160,6 +160,34 @@ struct DeviceType {
{
return InFamily(INTEL_FAMILY_SER5);
}
int Generation() const
{
if (InFamily(INTEL_FAMILY_7xx))
return 1;
if (InFamily(INTEL_FAMILY_8xx))
return 2;
if (InGroup(INTEL_GROUP_91x) || InGroup(INTEL_GROUP_94x)
|| IsModel(INTEL_MODEL_G33))
return 3;
if (InFamily(INTEL_FAMILY_9xx))
return 4;
if (InGroup(INTEL_GROUP_ILK))
return 5;
if (InGroup(INTEL_GROUP_SNB))
return 6;
if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_SLV))
return 7;
// TODO: Groups below here might need some tweaking
if (InGroup(INTEL_GROUP_AIR) || InGroup(INTEL_GROUP_GOL))
return 8;
// TODO: SkyLake, Broxton is gen 9
// Generation 0 means somethins is wrong :-)
return 0;
}
};
// info about PLL on graphics card

32
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
View File

@ -248,10 +248,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
frameBufferSize = 64 << 20;
else
frameBufferSize = 128 << 20;
} else if (info.type->InFamily(INTEL_FAMILY_9xx)
|| info.type->InFamily(INTEL_FAMILY_SER5)
|| info.type->InFamily(INTEL_FAMILY_SOC0)
|| info.type->InFamily(INTEL_FAMILY_POVR)) {
} else if (info.type->Generation() >= 3) {
frameBufferSize = info.display.u.h0.base_register_sizes[2];
}
@ -385,16 +382,22 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
static void
set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress)
{
if (info.type->InGroup(INTEL_GROUP_96x)
|| info.type->InGroup(INTEL_GROUP_Gxx)
|| info.type->InGroup(INTEL_GROUP_G4x)
|| info.type->InGroup(INTEL_GROUP_IGD)
|| info.type->InGroup(INTEL_GROUP_ILK)) {
// possible high bits are stored in the lower end
physicalAddress |= (physicalAddress >> 28) & 0x00f0;
} else if (info.type->InGroup(INTEL_GROUP_SNB)) {
if (info.type->Generation() >= 8) {
// Airmont, Goldmont
physicalAddress |= (physicalAddress >> 28) & 0x07f0;
// TODO: cache control?
} else if (info.type->Generation() >= 6) {
// SandyBridge, IronLake, IvyBridge, Haswell
physicalAddress |= (physicalAddress >> 28) & 0x0ff0;
physicalAddress |= 0x02; // cache control, l3 cacheable
} else if (info.type->Generation() >= 4) {
// Intel 9xx minus 91x, 94x, G33
// possible high bits are stored in the lower end
physicalAddress |= (physicalAddress >> 28) & 0x00f0;
// TODO: cache control?
}
// TODO: this is not 64-bit safe!
@ -419,10 +422,7 @@ intel_map(intel_info &info)
{
int fbIndex = 0;
int mmioIndex = 1;
if (info.type->InFamily(INTEL_FAMILY_9xx)
|| info.type->InFamily(INTEL_FAMILY_SER5)
|| info.type->InFamily(INTEL_FAMILY_SOC0)
|| info.type->InFamily(INTEL_FAMILY_POVR)) {
if (info.type->Generation() >= 3) {
// for some reason Intel saw the need to change the order of the
// mappings with the introduction of the i9xx family
mmioIndex = 0;