intel_extreme: fix pipe and plane size registers
- The name for the registers were swapped - The width and height were also swapped in one of them - Remove some old #if 0 code that touched these registers but has been disabled for a while.
This commit is contained in:
Adrien Destugues
parent
abcbfac601
commit
2beddbfd46
@ -549,8 +549,8 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT)
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// Cougar Point transcoder pipe selection
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#define PORT_TRANS_A_SEL_CPT 0
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@ -668,7 +668,7 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL)
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// reserved on A
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#define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL)
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// i965 and up only
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@ -676,7 +676,7 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL)
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#define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL)
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// i965 and up only
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@ -209,26 +209,22 @@ Pipe::ConfigureTimings(display_mode* target, bool hardware)
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| ((uint32)target->timing.v_sync_start - 1));
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}
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// XXX: Is it ok to do these on non-digital?
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write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
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// Set the image size for both pipes, just in case.
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write32(INTEL_DISPLAY_A_IMAGE_SIZE,
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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write32(INTEL_DISPLAY_B_IMAGE_SIZE,
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset,
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((uint32)(target->timing.v_display - 1) << 16)
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| ((uint32)target->timing.h_display - 1));
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((uint32)(target->timing.h_display - 1) << 16)
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| ((uint32)target->timing.v_display - 1));
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// This is useful for debugging: it sets the border to red, so you
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// can see what is border and what is porch (black area around the
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// sync)
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//write32(INTEL_DISPLAY_A_RED + fPipeOffset, 0x00FF0000);
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// Set the plane size as well while we're at it (this is independant, we
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// could have a larger plane and scroll through it).
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if (gInfo->shared_info->device_type.Generation() > 4) {
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// This is "reserved" on G45 and below.
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write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset,
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((uint32)(target->virtual_width - 1) << 16)
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| ((uint32)target->virtual_height - 1));
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}
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// Since we set the plane to be the same size as the display, we can just
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// show it starting at top-left.
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write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0);
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if (fHasTranscoder)
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_ConfigureTranscoder(target);
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@ -40,165 +40,6 @@
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#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
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#if 0
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// This hack needs to die. Leaving in for a little while
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// incase we *really* need it.
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static void
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retrieve_current_mode(display_mode& mode, uint32 pllRegister)
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{
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uint32 pll = read32(pllRegister);
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uint32 pllDivisor;
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uint32 hTotalRegister;
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uint32 vTotalRegister;
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uint32 hSyncRegister;
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uint32 vSyncRegister;
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uint32 imageSizeRegister;
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uint32 controlRegister;
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if (pllRegister == INTEL_DISPLAY_A_PLL) {
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pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0
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? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0);
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hTotalRegister = INTEL_DISPLAY_A_HTOTAL;
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vTotalRegister = INTEL_DISPLAY_A_VTOTAL;
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hSyncRegister = INTEL_DISPLAY_A_HSYNC;
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vSyncRegister = INTEL_DISPLAY_A_VSYNC;
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imageSizeRegister = INTEL_DISPLAY_A_IMAGE_SIZE;
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controlRegister = INTEL_DISPLAY_A_CONTROL;
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} else if (pllRegister == INTEL_DISPLAY_B_PLL) {
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pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0
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? INTEL_DISPLAY_B_PLL_DIVISOR_1 : INTEL_DISPLAY_B_PLL_DIVISOR_0);
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hTotalRegister = INTEL_DISPLAY_B_HTOTAL;
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vTotalRegister = INTEL_DISPLAY_B_VTOTAL;
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hSyncRegister = INTEL_DISPLAY_B_HSYNC;
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vSyncRegister = INTEL_DISPLAY_B_VSYNC;
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imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE;
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controlRegister = INTEL_DISPLAY_B_CONTROL;
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} else {
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ERROR("%s: PLL not supported\n", __func__);
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return;
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}
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pll_divisors divisors;
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
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divisors.m1 = 0;
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divisors.m2 = (pllDivisor & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)
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>> DISPLAY_PLL_M2_DIVISOR_SHIFT;
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divisors.n = ((pllDivisor & DISPLAY_PLL_IGD_N_DIVISOR_MASK)
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>> DISPLAY_PLL_N_DIVISOR_SHIFT) - 1;
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} else {
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divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK)
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>> DISPLAY_PLL_M1_DIVISOR_SHIFT;
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divisors.m2 = (pllDivisor & DISPLAY_PLL_M2_DIVISOR_MASK)
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>> DISPLAY_PLL_M2_DIVISOR_SHIFT;
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divisors.n = (pllDivisor & DISPLAY_PLL_N_DIVISOR_MASK)
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>> DISPLAY_PLL_N_DIVISOR_SHIFT;
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}
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pll_limits limits;
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get_pll_limits(&limits, false);
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// TODO: Detect LVDS connector vs assume no
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if (gInfo->shared_info->device_type.Generation() >= 3) {
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) {
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divisors.post1 = (pll & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT;
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} else {
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divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
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}
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if (pllRegister == INTEL_DISPLAY_B_PLL
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&& !gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) {
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// TODO: Fix this? Need to support dual channel LVDS.
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divisors.post2 = LVDS_POST2_RATE_SLOW;
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} else {
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if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0)
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divisors.post2 = limits.max.post2;
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else
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divisors.post2 = limits.min.post2;
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}
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} else {
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// 8xx
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divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
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if ((pll & DISPLAY_PLL_DIVIDE_4X) != 0)
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divisors.post2 = limits.max.post2;
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else
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divisors.post2 = limits.min.post2;
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}
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divisors.m = 5 * divisors.m1 + divisors.m2;
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divisors.post = divisors.post1 * divisors.post2;
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float referenceClock
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= gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
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float pixelClock
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= ((referenceClock * divisors.m) / divisors.n) / divisors.post;
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// timing
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mode.timing.pixel_clock = uint32(pixelClock * 1000);
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mode.timing.flags = 0;
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uint32 value = read32(hTotalRegister);
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mode.timing.h_total = (value >> 16) + 1;
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mode.timing.h_display = (value & 0xffff) + 1;
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value = read32(hSyncRegister);
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mode.timing.h_sync_end = (value >> 16) + 1;
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mode.timing.h_sync_start = (value & 0xffff) + 1;
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value = read32(vTotalRegister);
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mode.timing.v_total = (value >> 16) + 1;
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mode.timing.v_display = (value & 0xffff) + 1;
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value = read32(vSyncRegister);
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mode.timing.v_sync_end = (value >> 16) + 1;
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mode.timing.v_sync_start = (value & 0xffff) + 1;
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// image size and color space
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value = read32(imageSizeRegister);
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mode.virtual_width = (value >> 16) + 1;
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mode.virtual_height = (value & 0xffff) + 1;
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// using virtual size based on image size is the 'proper' way to do it,
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// however the bios appears to be suggesting scaling or somesuch, so ignore
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// the proper virtual dimension for now if they'd suggest a smaller size.
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if (mode.virtual_width < mode.timing.h_display)
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mode.virtual_width = mode.timing.h_display;
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if (mode.virtual_height < mode.timing.v_display)
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mode.virtual_height = mode.timing.v_display;
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value = read32(controlRegister);
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switch (value & DISPLAY_CONTROL_COLOR_MASK) {
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case DISPLAY_CONTROL_RGB32:
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default:
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mode.space = B_RGB32;
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break;
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case DISPLAY_CONTROL_RGB16:
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mode.space = B_RGB16;
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break;
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case DISPLAY_CONTROL_RGB15:
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mode.space = B_RGB15;
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break;
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case DISPLAY_CONTROL_CMAP8:
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mode.space = B_CMAP8;
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break;
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}
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mode.h_display_start = 0;
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mode.v_display_start = 0;
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mode.flags = B_8_BIT_DAC | B_HARDWARE_CURSOR | B_PARALLEL_ACCESS
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| B_DPMS | B_SUPPORTS_OVERLAYS;
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}
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#endif
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static void
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get_color_space_format(const display_mode &mode, uint32 &colorMode,
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uint32 &bytesPerRow, uint32 &bitsPerPixel)
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