intel_extreme: Implement Ilk PCH FDI link training
* IronLake tested and FDI says it trains successfully * Still no LVDS video on Ilk
This commit is contained in:
Alexander von Gluck IV
parent
9ca266967d
commit
c0d4def4e4
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@ -89,8 +89,8 @@
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#define INTEL_PCH_PPT_DEVICE_ID 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID 0x8c00
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#define INTEL_PCH_LPT_LP_DEVICE_ID 0x9c00
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#define INTEL_PCH_SPT_DEVICE_ID 0xA100
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#define INTEL_PCH_SPT_LP_DEVICE_ID 0x9D00
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#define INTEL_PCH_SPT_DEVICE_ID 0xa100
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#define INTEL_PCH_SPT_LP_DEVICE_ID 0x9d00
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#define INTEL_PCH_P2X_DEVICE_ID 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID 0x7000
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@ -543,21 +543,21 @@ struct intel_free_graphics_memory {
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#define PORT_TRANS_SEL_MASK (3<<29)
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// on PCH we also have to set the transcoder
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#define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HTOTAL (0x0000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HBLANK (0x0004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_HSYNC (0x0008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT)
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// TODO: Is there consolidation that could happen here with digital ports?
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@ -855,9 +855,26 @@ struct intel_free_graphics_memory {
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#define PCH_FDI_RX_BASE_REGISTER 0xf0000
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#define PCH_FDI_RX_PIPE_OFFSET 0x01000
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#define PCH_FDI_RX_CONTROL 0x00c
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#define PCH_FDI_RX_IIR 0x014
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#define PCH_FDI_RX_IMR 0x018
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#define FDI_RX_ENABLE (1 << 31)
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#define FDI_RX_PLL_ENABLED (1 << 13)
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// FDI_tX interrupt register
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#define FDI_RX_INTER_LANE_ALIGN (1 << 10)
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#define FDI_RX_SYMBOL_LOCK (1 << 9)
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#define FDI_RX_BIT_LOCK (1 << 8)
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#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7)
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#define FDI_RX_FS_CODE_ERR (1 << 6)
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#define FDI_RX_FE_CODE_ERR (1 << 5)
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#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4)
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#define FDI_RX_HDCP_LINK_FAIL (1 << 3)
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#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2)
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#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1)
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#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0)
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#define FDI_FS_ERRC_ENABLE (1 << 27)
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#define FDI_FE_ERRC_ENABLE (1 << 26)
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@ -871,12 +888,37 @@ struct intel_free_graphics_memory {
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#define FDI_RX_CLOCK_RAW (0 << 4)
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#define FDI_RX_CLOCK_PCD (1 << 4)
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#define PCH_FDI_TX_BASE_REGISTER 0x60000
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#define PCH_FDI_TX_PIPE_OFFSET 0x01000
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#define PCH_FDI_TX_CONTROL 0x100
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#define FDI_TX_ENABLE (1 << 31)
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#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
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#define FDI_TX_PLL_ENABLED (1 << 14)
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#define PCH_FDI_TX_BASE_REGISTER 0x60000
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#define PCH_FDI_TX_PIPE_OFFSET 0x01000
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#define PCH_FDI_TX_CONTROL 0x100
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#define FDI_TX_ENABLE (1 << 31)
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#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
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#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
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#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
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#define FDI_LINK_TRAIN_NONE (3 << 28)
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#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
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// SNB A stepping
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#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
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#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
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#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
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#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22)
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// SNB B stepping
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#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22)
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#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
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#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
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#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
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#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
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#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18)
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#define FDI_TX_PLL_ENABLED (1 << 14)
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#define FDI_DP_PORT_WIDTH_SHIFT 19
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#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
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@ -887,35 +929,9 @@ struct intel_free_graphics_memory {
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#define FDI_PLL_BIOS_1 0x46004
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#define FDI_PLL_BIOS_2 0x46008
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#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28)
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#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28)
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#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28)
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#define FDI_LINK_TRAIN_NONE (3 << 28)
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#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25)
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#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22)
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#define FDI_AUTO_TRAINING (1 << 10)
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#define FDI_AUTO_TRAIN_DONE (1 << 1)
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// SNB A-stepping
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#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
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#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
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#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
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#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x00 << 22)
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// SNB B-stepping
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#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x00 << 22)
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#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22)
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#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22)
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#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22)
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#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22)
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#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8)
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#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8)
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#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8)
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@ -928,6 +944,11 @@ struct intel_free_graphics_memory {
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#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8)
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#define FDI_LINK_TRAIN_NONE_IVB (3 << 8)
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#define PCH_FDI_RXA_CHICKEN (0x200c | REGS_SOUTH_SHARED)
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#define PCH_FDI_RXB_CHICKEN (0x2010 | REGS_SOUTH_SHARED)
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#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0)
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#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1)
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// CPU Panel Fitters - These are for IronLake and up and are the CPU internal
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// panel fitters.
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#define PCH_PANEL_FITTER_BASE_REGISTER 0x68000
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@ -220,7 +220,8 @@ FDIReceiver::SwitchClock(bool toPCDClock)
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FDILink::FDILink(pipe_index pipeIndex)
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:
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fTransmitter(pipeIndex),
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fReceiver(pipeIndex)
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fReceiver(pipeIndex),
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fPipeIndex(pipeIndex)
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{
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}
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@ -262,17 +263,172 @@ FDILink::Train(display_mode* target)
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status_t result = B_ERROR;
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// Over IVB supports AutoTraining of FDI
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if (gInfo->shared_info->device_type.Generation() >= 7) {
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// TODO: Only _AutoTrain on IVYB Stepping B or later
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// otherwise, _ManualTrain
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if (gInfo->shared_info->device_type.Generation() >= 7)
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result = _AutoTrain(lanes);
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if (result != B_OK) {
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ERROR("%s: FDI auto-training fault. Attempting manual train.\n",
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__func__);
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return _ManualTrain(lanes);
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}
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return B_OK;
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else if (gInfo->shared_info->device_type.Generation() == 6)
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result = _SnbTrain(lanes);
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else if (gInfo->shared_info->device_type.Generation() == 5)
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result = _IlkTrain(lanes);
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else
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result = _NormalTrain(lanes);
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if (result != B_OK) {
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ERROR("%s: FDI training fault.\n", __func__);
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}
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return _ManualTrain(lanes);
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return result;
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}
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status_t
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FDILink::_NormalTrain(uint32 lanes)
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{
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CALLED();
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uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
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uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
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// Enable normal link training
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uint32 tmp = read32(txControl);
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
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tmp &= ~FDI_LINK_TRAIN_NONE_IVB;
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tmp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
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} else {
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
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}
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write32(txControl, tmp);
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tmp = read32(rxControl);
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if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {
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tmp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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tmp |= FDI_LINK_TRAIN_NORMAL_CPT;
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} else {
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_NONE;
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}
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write32(rxControl, tmp | FDI_RX_ENHANCE_FRAME_ENABLE);
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// Wait 1x idle pattern
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read32(rxControl);
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spin(1000);
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// Enable ecc on IVB
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IVB)) {
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write32(rxControl, read32(rxControl)
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| FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
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read32(rxControl);
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}
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return B_OK;
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}
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status_t
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FDILink::_IlkTrain(uint32 lanes)
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{
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CALLED();
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uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
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uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
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// Train 1: unmask FDI RX Interrupt symbol_lock and bit_lock
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uint32 tmp = read32(Receiver().Base() + PCH_FDI_RX_IMR);
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tmp &= ~FDI_RX_SYMBOL_LOCK;
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tmp &= ~FDI_RX_BIT_LOCK;
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write32(Receiver().Base() + PCH_FDI_RX_IMR, tmp);
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spin(150);
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// Enable CPU FDI TX and RX
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tmp = read32(txControl);
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tmp &= ~FDI_DP_PORT_WIDTH_MASK;
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tmp |= FDI_DP_PORT_WIDTH(lanes);
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_PATTERN_1;
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write32(txControl, tmp);
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Transmitter().Enable();
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tmp = read32(rxControl);
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_PATTERN_1;
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write32(rxControl, tmp);
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Receiver().Enable();
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// ILK Workaround, enable clk after FDI enable
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if (fPipeIndex == INTEL_PIPE_B) {
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write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);
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write32(PCH_FDI_RXB_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR
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| FDI_RX_PHASE_SYNC_POINTER_EN);
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} else {
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write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR);
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write32(PCH_FDI_RXA_CHICKEN, FDI_RX_PHASE_SYNC_POINTER_OVR
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| FDI_RX_PHASE_SYNC_POINTER_EN);
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}
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uint32 iirControl = Receiver().Base() + PCH_FDI_RX_IIR;
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TRACE("%s: FDI RX IIR Control @ 0x%x\n", __func__, iirControl);
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int tries = 0;
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for (tries = 0; tries < 5; tries++) {
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tmp = read32(iirControl);
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TRACE("%s: FDI RX IIR 0x%x\n", __func__, tmp);
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if ((tmp & FDI_RX_BIT_LOCK)) {
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TRACE("%s: FDI train 1 done\n", __func__);
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write32(iirControl, tmp | FDI_RX_BIT_LOCK);
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break;
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}
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}
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if (tries == 5) {
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ERROR("%s: FDI train 1 failure!\n", __func__);
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return B_ERROR;
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}
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// Train 2
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tmp = read32(txControl);
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_PATTERN_2;
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write32(txControl, tmp);
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tmp = read32(rxControl);
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tmp &= ~FDI_LINK_TRAIN_NONE;
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tmp |= FDI_LINK_TRAIN_PATTERN_2;
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write32(rxControl, tmp);
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read32(rxControl);
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spin(150);
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for (tries = 0; tries < 5; tries++) {
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tmp = read32(iirControl);
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TRACE("%s: FDI RX IIR 0x%x\n", __func__, tmp);
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if (tmp & FDI_RX_SYMBOL_LOCK) {
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TRACE("%s: FDI train 2 done\n", __func__);
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write32(iirControl, tmp | FDI_RX_SYMBOL_LOCK);
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break;
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}
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}
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if (tries == 5) {
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ERROR("%s: FDI train 2 failure!\n", __func__);
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return B_ERROR;
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}
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return B_OK;
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}
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status_t
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FDILink::_SnbTrain(uint32 lanes)
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{
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CALLED();
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//uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
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//uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
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ERROR("%s: TODO\n", __func__);
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return B_ERROR;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -280,14 +436,12 @@ status_t
|
|||
FDILink::_ManualTrain(uint32 lanes)
|
||||
{
|
||||
CALLED();
|
||||
//uint32 txControl = Transmitter().Base() + PCH_FDI_TX_CONTROL;
|
||||
//uint32 rxControl = Receiver().Base() + PCH_FDI_RX_CONTROL;
|
||||
|
||||
// This needs completed
|
||||
ERROR("TODO: Manual FDI Link Training\n");
|
||||
ERROR("%s: TODO\n", __func__);
|
||||
|
||||
// Enable pipes
|
||||
Transmitter().Enable();
|
||||
Receiver().Enable();
|
||||
return B_OK;
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -68,11 +68,16 @@ public:
|
|||
status_t Train(display_mode* target);
|
||||
|
||||
private:
|
||||
status_t _NormalTrain(uint32 lanes);
|
||||
status_t _IlkTrain(uint32 lanes);
|
||||
status_t _SnbTrain(uint32 lanes);
|
||||
status_t _ManualTrain(uint32 lanes);
|
||||
status_t _AutoTrain(uint32 lanes);
|
||||
|
||||
FDITransmitter fTransmitter;
|
||||
FDIReceiver fReceiver;
|
||||
|
||||
pipe_index fPipeIndex;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -74,8 +74,7 @@ Pipe::Pipe(pipe_index pipeIndex)
|
|||
fHasTranscoder = true;
|
||||
|
||||
// Program FDILink if PCH
|
||||
if (fFDILink == NULL)
|
||||
fFDILink = new(std::nothrow) FDILink(pipeIndex);
|
||||
fFDILink = new(std::nothrow) FDILink(pipeIndex);
|
||||
}
|
||||
|
||||
TRACE("Pipe %s. Pipe Base: 0x%" B_PRIxADDR
|
||||
|
|
|
|||
|
|
@ -471,6 +471,11 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
|
|||
if (!wait_for_clear(panelStatus, PANEL_STATUS_POWER_ON, 1000))
|
||||
ERROR("%s: %s didn't power off within 1000ms!\n", __func__, PortName());
|
||||
|
||||
// Train FDI if it exists
|
||||
FDILink* link = fPipe->FDI();
|
||||
if (link != NULL)
|
||||
link->Train(target);
|
||||
|
||||
#if 0
|
||||
// Disable PanelFitter for now
|
||||
addr_t panelFitterControl = PCH_PANEL_FITTER_BASE_REGISTER
|
||||
|
|
|
|||
Loading…
Reference in New Issue