* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.
parameters from first principles rather than using a static table for some
rates. This makes it work correctly on ARM7500, for which the table was
bogus (ARM7500 has a different refclk from VIDC20).
Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true. Also appears we're actually missing some, eg the ld block device.
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
The tmpx registers are now outputs, this makes them all unique.
Add the fact that cc is changed by the asm (not believed to be used but rather be correct)
Correctly specify w as an input and output register, I think this was hiding the bug below!
Allow sum to be in a different input and output register.
Correct bug in psuedo header handling for in4_cksum. Seems that the new macros turned up a latent bug in the psuedo header handling, the code was moving a pointer forward 16 bytes twice, not found before as the ADD16 macro wasn't 100% accurate, as it didn't output w, even though it modified it.
only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).
Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".
not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups
pre-B-step errata: must clean-dcache-line to an address before
invalidate-dcache-line to that address, or the dirty bits will not
get cleanred in the dcache array for that line.
broke too many assumptions makde by other parts of the source tree,
and the strategy and how it was supposed to work was never discussed
on tech-userlevel, nor was it applied consistently (to all ARM ports
and to other ports which have common MACHINE_ARCH code, such as MIPS,
m68k, powerpc).
Verified to complete a full "make build" on cats, dnard, evbarm,
and netwinder.
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.
- replace opt_kgdb_machdep.h with opt_kgdb.h
- defparam opt_kgdb.h:
KGDB_DEV KGDB_DEVNAME KGDB_DEVADDR KGDB_DEVRATE KGDB_DEVMODE
- move from opt_ddbparam.h to opt_ddb.h:
DDB_FROMCONSOLE DDB_ONPANIC DDB_HISTORY_SIZE DDB_BREAK_CHAR SYMTAB_SPACE
- replace KGDBDEV with KGDB_DEV
- replace KGDBADDR with KGDB_DEVADDR
- replace KGDBMODE with KGDB_DEVMODE
- replace KGDBRATE with KGDB_DEVRATE
- use `9600' instead of `0x2580' for 9600 baud rate
- use correct quotes for options KGDB_DEVNAME="\"com\""
- use correct quotes for options KGDB_DEV="17*256+0"
- remove unnecessary dependancy on Makefile for kgdb_stub.o
- minor whitespace cleanup
switch_exit only needs to take 1 parameter, it loads the value of proc0 into R1 itself
Fixup some comments to reflect the real state of things.
Tweak a couple of bits of asm to avoid a load delay.
remove excess code for setting curpcb and curproc.
this insn is available only on ARM arch v3 and later (and 2a). We
don't expect to be using these ops in the kernel on processors too
old to have SWP, and for userland uses (in e.g. a pthread library),
the kernel will simply have to trap and emulate the insn (it needs
to be "atomic", so a kernel trap of some sort will be necessary on
such platforms anyway).
the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
manual (section 5.1, Branch Target Buffer Operation) notes that
manual software management of the BTB is unnecessary; it is flushed
implicitly when:
* processor resets
* FCSE process ID is written
* I-cache is invalidated
* sa110_cache_purgeD() is the same as sa110_cache_cleanD() on the
SA-1 -- make it an alias.
* sa110_cache_syncI() and sa110_cache_purgeID() are identical to
sa110_cache_cleanD() on the SA-1, with the exception that the
I-cache must also be flushed. Save code duplication by moving
the I-cache flush before the D-cache clean and letting it fall
through.
* Define a CPWAIT macro as described in the i80200 manual and use it,
rather than replicating the code in a few places.
* The i80200 manual notes that the line-allocate operation used to
do global D$ clean does not actually perform a load/fill request
from external memory, and thus does not actually place valid data
in the cache lines allocated. Require that machine-dependent code
allocate an appropriately-sized chunk of unmapped VA space for the
global clean operation in order to avoid unpredictable results.
* The i80200 manual notes that the VA range for the Mini-Data global
clean (which *must* be mapped to physical memory) must be reserved
exclusively for cleaning the Mini-Data cache. Require that machine-
dependent code allocate an appropriately-sized chunk of memory for
this purpose.
pages, we use the standard (4K) page size as PAGE_SIZE. Make the
PAGE_SIZE related variables compile-time constants that reflect this.
Results in a bit over 2K worth of .text savings, and visibly better
code in the places that use PAGE_SIZE, etc.
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.
Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE. On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.
we need later in the code. This fixes a fatal kernel fault in
pmap_modified_emulation if a user application tries to access a kernel
address that is section-mapped.
Add a diagnostic that detects attempts to call pmap_kenter_pa with a
va that is section-mapped.
caching on for a page just because we are clearing the writable bit in
the PTE: this is incompatible with the way pmap_vac_me_harder works,
and the code in the modified emulation handler doesn't know about
recalculating the cachable attributes (nor should it, IMO).
Also, if we are invalidating a page, flush its TLB entry; for some
reason we were only doing this when clearing the Write or modified
bits.
These patches together seem to solve the random seg-faults that were
still occuring occasionally under heavy paging.
is higher than SPL_HIGH (maybe we should be fixing SPL_HIGH).
If IPL_STATCLOCK is defined, initialize spl_masks[_SPL_STATCLOCK] from
it; otherwise initialize use IPL_CLOCK.
the etc Makefile override that by putting USETOOLS into $.MAKEOVERRIDES
This way the default for kernel compiles is still to use the installed
toolchain instead of depending on $TOOLDIR. $TOOLDIR can be used by
simply adding USETOOLS=yes to the command line as usual.
Adjust each ports template to set the default no setting and also pull in
bsd.own.mk if they weren't already to ensure they'll build correctly
with the new toolchain setup.
support it in the kernel yet. If we don't do this, GDB arbitrarily
assumes we wanted it to be 9, which is silly.
In the kernel, leave it undefined so that sys_process.c doesn't
generate code for it.
the instruction we used with GDB 4.x. The new instruction has the advantage
of fitting the pattern that ARM recommend using for instructions that need to
stay undefined.
(eg ARM920), the mode in which the processor operates is governed by
the use of both the PT_C and PT_B bits:
PT_C=1,PT_B=1 -> Write-back
PT_C=1,PT_B=0 -> Write-through
To support this define pte_cache_mode (initialized to PT_C|PT_B) and
use that when enabling cacheing for a page.
to allocate a L1 pt is often enough to bring the system to its knees:
so make the messages PDEBUG(0,...).
However, even with this step having more than a small number of
processes searching for a L1 pt can still be enough to bring the system
down, since they all run at high priority and sleep for very little time,
thus blocking out user code from completing. So implement an exponential
backoff when waiting for a page table, so that we don't hog the CPU when
memory is scarce.
Tested by running a make of the C compiler with "gnumake -j30" (and plenty
of swap space).
is shared with another process (as can happen if vfork is being used),
then that other process will end up not having a page 0, which is bad
news indeed, since then there is no way back into the kernel.
Found this using a multi-ice box, so they are useful after all!
This seems to fix pr port-arm32/11921 and (possibly) kern/9859.
arch/arm/iomd/* .... the RC7500 isnt really an iomd/vidc machine but has
different video/audio chip and was kind of hardwired/hacked into the other
chip drivers.
The IOMD/VIDC combination is now moved to arch/arm/iomd together. These
files still need a lot of cleaning up :( .... esp. the RC7500 support that
is still dormant in it; this needs either to be removed or split out for
RC7500's ``VIDC'' video/audio variant.
Apart from the RC7500 support wich is still in arch/arm32 the
iomd,vidc,riscpc and podulebus subdirectories of arch/arm32 can be removed.
This split still uses some small parts of arch/arm32 .... those are the MI
parts that haven't been moved yet.
RiscPC/A7000 have been tested and confirmed to build as should NC.
- remove special treatment of pager_map mappings in pmaps. this is
required now, since I've removed the globals that expose the address range.
pager_map now uses pmap_kenter_pa() instead of pmap_enter(), so there's
no longer any need to special-case it.
- eliminate struct uvm_vnode by moving its fields into struct vnode.
- rewrite the pageout path. the pager is now responsible for handling the
high-level requests instead of only getting control after a bunch of work
has already been done on its behalf. this will allow us to UBCify LFS,
which needs tighter control over its pages than other filesystems do.
writing a page to disk no longer requires making it read-only, which
allows us to write wired pages without causing all kinds of havoc.
- use a new PG_PAGEOUT flag to indicate that a page should be freed
on behalf of the pagedaemon when it's unlocked. this flag is very similar
to PG_RELEASED, but unlike PG_RELEASED, PG_PAGEOUT can be cleared if the
pageout fails due to eg. an indirect-block buffer being locked.
this allows us to remove the "version" field from struct vm_page,
and together with shrinking "loan_count" from 32 bits to 16,
struct vm_page is now 4 bytes smaller.
- no longer use PG_RELEASED for swap-backed pages. if the page is busy
because it's being paged out, we can't release the swap slot to be
reallocated until that write is complete, but unlike with vnodes we
don't keep a count of in-progress writes so there's no good way to
know when the write is done. instead, when we need to free a busy
swap-backed page, just sleep until we can get it busy ourselves.
- implement a fast-path for extending writes which allows us to avoid
zeroing new pages. this substantially reduces cpu usage.
- encapsulate the data used by the genfs code in a struct genfs_node,
which must be the first element of the filesystem-specific vnode data
for filesystems which use genfs_{get,put}pages().
- eliminate many of the UVM pagerops, since they aren't needed anymore
now that the pager "put" operation is a higher-level operation.
- enhance the genfs code to allow NFS to use the genfs_{get,put}pages
instead of a modified copy.
- clean up struct vnode by removing all the fields that used to be used by
the vfs_cluster.c code (which we don't use anymore with UBC).
- remove kmem_object and mb_object since they were useless.
instead of allocating pages to these objects, we now just allocate
pages with no object. such pages are mapped in the kernel until they
are freed, so we can use the mapping to find the page to free it.
this allows us to remove splvm() protection in several places.
The sum of all these changes improves write throughput on my
decstation 5000/200 to within 1% of the rate of NetBSD 1.5
and reduces the elapsed time for "make release" of a NetBSD 1.5
source tree on my 128MB pc to 10% less than a 1.5 kernel took.
Remove some overzealous locking of HEAD_TO_MAP
Remove a potential deadlock in pmap_copy_page
Change alloc and free l1pt to use kenter/kremove.
Update pmap_map to use kenter (only actually used by dumpsys, so no matching kremove)
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.
Currently this is a no-op on most platforms, so they should see no difference.
Reviewed by Jason.
Thorpe as an extension to the bus_space(9) API.
Only the mainbus has a working mmap... iomd, podulebus and isa dont have
one yet. Its trivial to add the iomd and isa's memory part but am a bit
hessistant to add it without knowing its implications by heart.
Podulebus might be implemented in 32 bits EASI but otherwise its not really
transparent since there is AFAIK no function to explicitly read one byte or
so .. or is this implemented in a higher level ?
ARM26 and arch/arm32/dnard (Shark) kernels compile and RiscPC and Shark
kernels are tested and function OK.
Implications of other ARM systems like hpcarm and ebarm are propably
minimal or solved trivially.
ELF _C_LABEL(irqhandlers) == irqhandlers so we were getting self-referential
pointer which causes the IRQ to fall on itself. [With this change the
netwinder kernel can now be *ELF* and boots to multiuser]
Improved locking (not that we actually use it on a uniprocessor, but one day :)
Removed unneeded splvm's
tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E)
Adopted pv entry allocation mechanism from i386.
Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits.
ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove.
Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this.
I believe this code to be stable, if anyone has any problems please shout up.
little endian like order, however, usage of 'HPCFB_SWAP_*' was widely
misunderstood because it reminded you of 'RI_BSWAP' in raster operation.
Please note that 'RI_BSWAP' indicate that frame buffer byte order is different
from natural order of system while 'HPCFB_REVORDER_*' is independent of
system byte order.
bootable GENERAL kernel for the 3 machines.
This is done by integrating the ARM7500 in a better way. In various places
the IOMD ID is checked and action is taken at runtime compared to
compiletime.
The small piece of assembler that is changed now uses the flag
`arm7500_ioc_found' that is set up by iomd.c at startup. When this chip
isnt found at startup it will skip reading the ARM7500 extended IRQ
registers and wont clear them either.
The next step will be getting the mode-definition files to the bootloader.
Currently they are compiled in.
Note that I've some ideas in the works on how to improve the pv handling, so the slow down is short term only.
Also added non-advertising licence and copyright to myself and richard.
Update some of the functions that use pmap_pte to pmap_map_ptes.
Note that there's a dummy macro for pmap_unmap_ptes, this is because at some point locking will be needed, so we need to be able to unlock them.
Performance gain seems to be minimal, however long term it should help improve things.
This is similair to the i386 pmap_map_ptes, however it's based on a version from Richard Earnshaw.
Move the files from footbridge that are cats specific.
Remove EBSA285 kernel as people should be able to use the generic cats kernel for EBSA285 systems.
in arm/arm. This version is based on the arm26 version, and includes dumping
the contents of stack frames, with automatic determination of the save code
pointer offset.
instruction that stores the program counter and the value of PC that's stored.
This can vary between ARM implementations, but is guaranteed to be constant on
a given one.
early_abort_fixup() and late_abort_fixup(), have the latter tail-call the
former. This saves another 200 bytes, and I've found my ARM710a card now, so
I've even tested it.
and late_abort_fixup(), based on the abort model in use, rather than the CPU
type. This cleans up the code and makes it smaller. Only tested on an
ARM6 -- I can't find my ARM710a card right now.
- use "U" suffix for unsigned constants
- use "L" suffix for long constants
- use "UL" suffix for unsigned long constants
- use hexadecimal instead of decimal
Fixes build problems with vi (now that warnings/errors are enabled) on
mips, powerpc and arm platforms.
to <sys/types.h> and <sys/stdint.h>.
* Add a new C99 <stdint.h> header, which provides integer types of
explicit width, related limits and integer constant macros.
* Extend <inttypes.h> to provide <stdint.h> definitions and format
macros for printf() and scanf().
* Add C99 strtoimax() and strtoumax() functions.
* Use the latter within scanf().
* Add C99 %j, %t and %z printf()/scanf() conversions for
intmax_t, pointer-type and size_t arguments.
- pmap_enter()
- pmap_remove()
- pmap_protect()
- pmap_kenter_pa()
- pmap_kremove()
as described in pmap(9).
These calls are relatively conservative. It may be possible to
optimize these a little more.
always points to the undefined instruction in question. It's up to the
handler to advance it to the next instruction if it wants execution to
continue there. This is how things have always worked on arm26.
co-processor. This is necessary so we can have several handlers for
CP0 (used as a catch-all for non-CP instructions).
Handlers are now removed using remove_coproc_handler(), rather than by calling
install_coproc_handler() with a NULL handler.
Because install_coproc_handler() can now allocate memory, there's a version
for use at boot time that doesn't.
support, which corresponds to one for each CPU_* option, or one for each
cpufunc structure.
Also remove some more residual code for the support of multiple and non-ARM
CPUs.
is derived mostly from the arm32 version, but with a check for an obscure ARM2
bug thrown in.
arm26 fpu and cpu drivers use the new interface for catching undefined
instructions.
thorpej