Snapshot of work-in-progress for Intel i80312 Companion I/O chip;
just basic Inbound and Outbound window setup is done, PCI configuration space access (not quite working yet), and I/O and Memory space routines so far.
This commit is contained in:
thorpej
parent
411b3e63cf
commit
660b98b7dc
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@ -1,6 +1,13 @@
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# $NetBSD: files.i80312,v 1.1 2001/11/05 23:38:55 thorpej Exp $
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# $NetBSD: files.i80312,v 1.2 2001/11/09 03:27:51 thorpej Exp $
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#
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# Configuration info for Intel i80312 Companion I/O support
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#
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file arch/arm/xscale/i80312_mem.c
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device iopxs: pcibus
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# Board-specific front-end provides attachment.
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file arch/arm/xscale/i80312.c iopxs
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file arch/arm/xscale/i80312_pci.c iopxs
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file arch/arm/xscale/i80312_space.c iopxs
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file arch/arm/xscale/i80312_space_asm.S iopxs
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@ -0,0 +1,267 @@
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/* $NetBSD: i80312.c,v 1.1 2001/11/09 03:27:51 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
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||||
* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Autoconfiguration support for the Intel i80312 Companion I/O chip.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <arm/xscale/i80312reg.h>
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#include <arm/xscale/i80312var.h>
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#include <dev/pci/ppbreg.h>
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/*
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* Statically-allocated bus_space stucture used to access the
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* i80312's own registers.
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*/
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struct bus_space i80312_bs_tag;
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int i80312_pcibus_print(void *, const char *);
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/*
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* i80312_attach:
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*
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* Board-independent attach routine for the i80312.
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*/
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void
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i80312_attach(struct i80312_softc *sc)
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{
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struct pcibus_attach_args pba;
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uint32_t atucr;
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pcireg_t preg;
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/*
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* Slice off some useful subregion handles.
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*/
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE,
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I80312_PPB_SIZE, &sc->sc_ppb_sh))
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panic("%s: unable to subregion PPB registers\n",
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sc->sc_dev.dv_xname);
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE,
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I80312_ATU_SIZE, &sc->sc_atu_sh))
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panic("%s: unable to subregion ATU registers\n",
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sc->sc_dev.dv_xname);
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/*
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* Disable the private space decode.
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*/
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sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh,
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I80312_PPB_SDER);
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sc->sc_sder &= ~PPB_SDER_PMSE;
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bus_space_write_1(sc->sc_st, sc->sc_ppb_sh,
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I80312_PPB_SDER, sc->sc_sder);
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/*
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* Program the Secondary ID Select register.
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*/
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bus_space_write_2(sc->sc_st, sc->sc_ppb_sh,
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I80312_PPB_SISR, sc->sc_sisr);
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/*
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* Program the private secondary bus spaces.
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*/
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if (sc->sc_privmem_size && sc->sc_privio_size) {
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bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR,
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(sc->sc_privio_base >> 12) << 4);
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bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR,
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((sc->sc_privio_base + sc->sc_privio_size - 1)
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>> 12) << 4);
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bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR,
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(sc->sc_privmem_base >> 20) << 4);
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bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR,
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((sc->sc_privmem_base + sc->sc_privmem_size - 1)
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>> 20) << 4);
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sc->sc_sder |= PPB_SDER_PMSE;
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bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER,
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sc->sc_sder);
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} else if (sc->sc_privmem_size || sc->sc_privio_size) {
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printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n",
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sc->sc_dev.dv_xname, sc->sc_privmem_size,
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sc->sc_privio_size);
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printf("%s: private bus spaces not enabled\n",
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sc->sc_dev.dv_xname);
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}
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/*
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* Program the Primary Inbound window.
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*/
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if (sc->sc_is_host)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START, sc->sc_pin_base);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size));
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_PIATV, sc->sc_pin_xlate);
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/*
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* Program the Secondary Inbound window.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SIAM, sc->sc_sin_base);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size));
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SIATV, sc->sc_sin_xlate);
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/*
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* Clear:
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*
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* Primary Outbound ATU Enable
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* Secondary Outbound ATU Enable
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* Secondary Direct Addressing Select
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* Direct Addressing Enable
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*/
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atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR);
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atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE);
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/*
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* Program the Primary Outbound windows.
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*/
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if (sc->sc_pmemout_size)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_POMWV, sc->sc_pmemout_base);
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if (sc->sc_pioout_size)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_POIOWV, sc->sc_pioout_base);
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if (sc->sc_pmemout_size || sc->sc_pioout_size)
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atucr |= ATU_ACR_POAE;
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/*
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* Program the Secondary Outbound windows.
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*/
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if (sc->sc_smemout_size)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SOMWV, sc->sc_smemout_base);
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if (sc->sc_sioout_size)
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SOIOWV, sc->sc_sioout_base);
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if (sc->sc_smemout_size || sc->sc_sioout_size)
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atucr |= ATU_ACR_SOAE;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr);
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/*
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* Enable bus mastering, memory access, SERR, and parity
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* checking on the ATU.
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*/
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if (sc->sc_is_host) {
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preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
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PCI_COMMAND_STATUS_REG);
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preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_COMMAND_STATUS_REG, preg);
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}
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preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SACS);
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preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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I80312_ATU_SACS, preg);
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/*
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* Configure the bridge. If we're a host, set the primary
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* bus to bus #0 and the secondary bus to bus #1. We also
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* set the PPB's subordinate bus # to 1. It will be fixed
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* up later when we fully configure the bus.
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*
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* If we're a slave, just use the bus #'s that the host
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* provides.
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*/
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_ppb_sh,
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PPB_REG_BUSINFO,
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(0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) |
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(1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) |
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(1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT));
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}
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/*
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* Initialize the bus space and DMA tags and the PCI chipset tag.
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*/
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i80312_io_bs_init(&sc->sc_pci_iot, sc);
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i80312_mem_bs_init(&sc->sc_pci_memt, sc);
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#if 0
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i80312_pci_dma_init(&sc->sc_pci_dmat, sc);
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#endif
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i80312_pci_init(&sc->sc_pci_chipset, sc);
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/*
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* Attach the PCI bus. Note that if we're a host, we can
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* safely probe for devices on the Primary bus. If we're
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* a slave, we must limit ourselves to our Secondary bus,
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* specifically, the private devices on the Secondary bus.
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*/
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pba.pba_busname = "pci";
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pba.pba_iot = &sc->sc_pci_iot;
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pba.pba_memt = &sc->sc_pci_memt;
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pba.pba_dmat = &sc->sc_pci_dmat;
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pba.pba_pc = &sc->sc_pci_chipset;
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pba.pba_bus = 1; /* XXX for now */
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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(void) config_found(&sc->sc_dev, &pba, i80312_pcibus_print);
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}
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/*
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* i80312_pcibus_print:
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*
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* Autoconfiguration cfprint routine when attaching
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* to the "pcibus" attribute.
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*/
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int
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i80312_pcibus_print(void *aux, const char *pnp)
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{
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struct pcibus_attach_args *pba = aux;
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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@ -0,0 +1,218 @@
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/* $NetBSD: i80312_pci.c,v 1.1 2001/11/09 03:27:51 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
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* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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/*
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* PCI configuration support for i80312 Companion I/O chip.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <arm/xscale/i80312reg.h>
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#include <arm/xscale/i80312var.h>
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#include <dev/pci/ppbreg.h>
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void i80312_pci_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int i80312_pci_bus_maxdevs(void *, int);
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pcitag_t i80312_pci_make_tag(void *, int, int, int);
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void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *,
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int *);
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pcireg_t i80312_pci_conf_read(void *, pcitag_t, int);
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void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t);
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#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
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#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
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void
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i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
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{
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pc->pc_conf_v = cookie;
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pc->pc_attach_hook = i80312_pci_attach_hook;
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pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
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pc->pc_make_tag = i80312_pci_make_tag;
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pc->pc_decompose_tag = i80312_pci_decompose_tag;
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pc->pc_conf_read = i80312_pci_conf_read;
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pc->pc_conf_write = i80312_pci_conf_write;
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}
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void
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i80312_pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* Nothing to do. */
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}
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int
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i80312_pci_bus_maxdevs(void *v, int busno)
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{
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return (32);
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}
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pcitag_t
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i80312_pci_make_tag(void *v, int b, int d, int f)
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{
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return ((b << 16) | (d << 11) | (f << 8));
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}
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void
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i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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struct pciconf_state {
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bus_addr_t ps_addr_reg;
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bus_addr_t ps_data_reg;
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uint32_t ps_addr_val;
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int ps_b, ps_d, ps_f;
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};
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static int
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i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset,
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struct pciconf_state *ps)
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{
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pcireg_t binfo;
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int pbus, sbus;
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i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
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binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
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pbus = PPB_BUSINFO_PRIMARY(binfo);
|
||||
sbus = PPB_BUSINFO_SECONDARY(binfo);
|
||||
|
||||
/*
|
||||
* If the bus # is the Primary bus #, use the Primary
|
||||
* Address/Data registers, otherwise use the Secondary
|
||||
* Address/Data registers.
|
||||
*/
|
||||
if (ps->ps_b == pbus) {
|
||||
ps->ps_addr_reg = I80312_ATU_POCCA;
|
||||
ps->ps_data_reg = I80312_ATU_POCCD;
|
||||
} else {
|
||||
ps->ps_addr_reg = I80312_ATU_SOCCA;
|
||||
ps->ps_data_reg = I80312_ATU_SOCCD;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the bus # is the Primary or Secondary bus #, then use
|
||||
* Type 0 cycles, else use Type 1.
|
||||
*
|
||||
* XXX We should filter out all non-private devices here!
|
||||
* XXX How does private space interact with PCI-PCI bridges?
|
||||
*/
|
||||
if (ps->ps_b == pbus || ps->ps_b == sbus) {
|
||||
if (ps->ps_d > (31 - 11))
|
||||
return (1);
|
||||
ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) |
|
||||
offset;
|
||||
} else {
|
||||
/* The tag is already in the correct format. */
|
||||
ps->ps_addr_val = tag | offset | 1;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
pcireg_t
|
||||
i80312_pci_conf_read(void *v, pcitag_t tag, int offset)
|
||||
{
|
||||
struct i80312_softc *sc = v;
|
||||
struct pciconf_state ps;
|
||||
vaddr_t va;
|
||||
pcireg_t rv;
|
||||
u_int s;
|
||||
|
||||
if (i80312_pci_conf_setup(sc, tag, offset, &ps))
|
||||
return ((pcireg_t) -1);
|
||||
|
||||
PCI_CONF_LOCK(s);
|
||||
|
||||
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
|
||||
ps.ps_addr_val);
|
||||
|
||||
#if 1
|
||||
va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh);
|
||||
if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) {
|
||||
printf("conf_read: %d/%d/%d bad address\n",
|
||||
ps.ps_b, ps.ps_d, ps.ps_f);
|
||||
rv = (pcireg_t) -1;
|
||||
}
|
||||
#else
|
||||
rv = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg);
|
||||
#endif
|
||||
|
||||
PCI_CONF_UNLOCK(s);
|
||||
|
||||
return (rv);
|
||||
}
|
||||
|
||||
void
|
||||
i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
|
||||
{
|
||||
struct i80312_softc *sc = v;
|
||||
struct pciconf_state ps;
|
||||
u_int s;
|
||||
|
||||
if (i80312_pci_conf_setup(sc, tag, offset, &ps))
|
||||
return;
|
||||
|
||||
PCI_CONF_LOCK(s);
|
||||
|
||||
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg,
|
||||
ps.ps_addr_val);
|
||||
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val);
|
||||
|
||||
PCI_CONF_UNLOCK(s);
|
||||
}
|
||||
|
|
@ -0,0 +1,360 @@
|
|||
/* $NetBSD: i80312_space.c,v 1.1 2001/11/09 03:27:51 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Wasabi Systems, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed for the NetBSD Project by
|
||||
* Wasabi Systems, Inc.
|
||||
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
|
||||
* or promote products derived from this software without specific prior
|
||||
* written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* bus_space functions for i80312 Companion I/O chip.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
#include <uvm/uvm_extern.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <arm/xscale/i80312var.h>
|
||||
|
||||
/* Prototypes for all the bus_space structure functions */
|
||||
bs_protos(i80312);
|
||||
bs_protos(i80312_io);
|
||||
bs_protos(i80312_mem);
|
||||
bs_protos(bs_notimpl);
|
||||
|
||||
/*
|
||||
* Template bus_space -- copied, and the bits that are NULL are
|
||||
* filled in.
|
||||
*/
|
||||
const struct bus_space i80312_bs_tag_template = {
|
||||
/* cookie */
|
||||
(void *) 0,
|
||||
|
||||
/* mapping/unmapping */
|
||||
NULL,
|
||||
NULL,
|
||||
i80312_bs_subregion,
|
||||
|
||||
/* allocation/deallocation */
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
/* get kernel virtual address */
|
||||
i80312_bs_vaddr,
|
||||
|
||||
/* mmap */
|
||||
i80312_bs_mmap,
|
||||
|
||||
/* barrier */
|
||||
i80312_bs_barrier,
|
||||
|
||||
/* read (single) */
|
||||
i80312_bs_r_1,
|
||||
i80312_bs_r_2,
|
||||
i80312_bs_r_4,
|
||||
bs_notimpl_bs_r_8,
|
||||
|
||||
/* read multiple */
|
||||
i80312_bs_rm_1,
|
||||
i80312_bs_rm_2,
|
||||
i80312_bs_rm_4,
|
||||
bs_notimpl_bs_rm_8,
|
||||
|
||||
/* read region */
|
||||
bs_notimpl_bs_rr_1,
|
||||
i80312_bs_rr_2,
|
||||
i80312_bs_rr_4,
|
||||
bs_notimpl_bs_rr_8,
|
||||
|
||||
/* write (single) */
|
||||
i80312_bs_w_1,
|
||||
i80312_bs_w_2,
|
||||
i80312_bs_w_4,
|
||||
bs_notimpl_bs_w_8,
|
||||
|
||||
/* write multiple */
|
||||
i80312_bs_wm_1,
|
||||
i80312_bs_wm_2,
|
||||
i80312_bs_wm_4,
|
||||
bs_notimpl_bs_wm_8,
|
||||
|
||||
/* write region */
|
||||
bs_notimpl_bs_wr_1,
|
||||
i80312_bs_wr_2,
|
||||
i80312_bs_wr_4,
|
||||
bs_notimpl_bs_wr_8,
|
||||
|
||||
/* set multiple */
|
||||
bs_notimpl_bs_sm_1,
|
||||
bs_notimpl_bs_sm_2,
|
||||
bs_notimpl_bs_sm_4,
|
||||
bs_notimpl_bs_sm_8,
|
||||
|
||||
/* set region */
|
||||
bs_notimpl_bs_sr_1,
|
||||
i80312_bs_sr_2,
|
||||
bs_notimpl_bs_sr_4,
|
||||
bs_notimpl_bs_sr_8,
|
||||
|
||||
/* copy */
|
||||
bs_notimpl_bs_c_1,
|
||||
i80312_bs_c_2,
|
||||
bs_notimpl_bs_c_4,
|
||||
bs_notimpl_bs_c_8,
|
||||
};
|
||||
|
||||
void
|
||||
i80312_bs_init(bus_space_tag_t bs, void *cookie)
|
||||
{
|
||||
|
||||
*bs = i80312_bs_tag_template;
|
||||
bs->bs_cookie = cookie;
|
||||
}
|
||||
|
||||
void
|
||||
i80312_io_bs_init(bus_space_tag_t bs, void *cookie)
|
||||
{
|
||||
|
||||
*bs = i80312_bs_tag_template;
|
||||
bs->bs_cookie = cookie;
|
||||
|
||||
bs->bs_map = i80312_io_bs_map;
|
||||
bs->bs_unmap = i80312_io_bs_unmap;
|
||||
bs->bs_alloc = i80312_io_bs_alloc;
|
||||
bs->bs_free = i80312_io_bs_free;
|
||||
|
||||
bs->bs_vaddr = i80312_io_bs_vaddr;
|
||||
}
|
||||
|
||||
void
|
||||
i80312_mem_bs_init(bus_space_tag_t bs, void *cookie)
|
||||
{
|
||||
|
||||
*bs = i80312_bs_tag_template;
|
||||
bs->bs_cookie = cookie;
|
||||
|
||||
bs->bs_map = i80312_mem_bs_map;
|
||||
bs->bs_unmap = i80312_mem_bs_unmap;
|
||||
bs->bs_alloc = i80312_mem_bs_alloc;
|
||||
bs->bs_free = i80312_mem_bs_free;
|
||||
|
||||
bs->bs_mmap = i80312_mem_bs_mmap;
|
||||
}
|
||||
|
||||
/* *** Routines shared by i80312, PCI IO, and PCI MEM. *** */
|
||||
|
||||
int
|
||||
i80312_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t size, bus_space_handle_t *nbshp)
|
||||
{
|
||||
|
||||
*nbshp = bsh + offset;
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
i80312_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
|
||||
bus_size_t len, int flags)
|
||||
{
|
||||
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
void *
|
||||
i80312_bs_vaddr(void *t, bus_space_handle_t bsh)
|
||||
{
|
||||
|
||||
return ((void *)bsh);
|
||||
}
|
||||
|
||||
paddr_t
|
||||
i80312_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
|
||||
{
|
||||
|
||||
/* Not supported. */
|
||||
return (-1);
|
||||
}
|
||||
|
||||
/* *** Routines for PCI IO. *** */
|
||||
|
||||
int
|
||||
i80312_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
|
||||
bus_space_handle_t *bshp)
|
||||
{
|
||||
struct i80312_softc *sc = t;
|
||||
vaddr_t winvaddr;
|
||||
uint32_t busbase, bussize;
|
||||
|
||||
if (bpa >= sc->sc_pioout_base &&
|
||||
bpa < (sc->sc_pioout_base + sc->sc_pioout_size)) {
|
||||
busbase = sc->sc_pioout_base;
|
||||
bussize = sc->sc_pioout_size;
|
||||
winvaddr = sc->sc_piow_vaddr;
|
||||
} else if (bpa >= sc->sc_sioout_base &&
|
||||
bpa < (sc->sc_sioout_base + sc->sc_sioout_size)) {
|
||||
busbase = sc->sc_sioout_base;
|
||||
bussize = sc->sc_sioout_size;
|
||||
winvaddr = sc->sc_siow_vaddr;
|
||||
} else
|
||||
return (EINVAL);
|
||||
|
||||
if ((bpa + size) >= (busbase + bussize))
|
||||
return (EINVAL);
|
||||
|
||||
/*
|
||||
* Found the window -- PCI I/O space is mapped at a fixed
|
||||
* virtual address by board-specific code. Translate the
|
||||
* bus address to the virtual address.
|
||||
*/
|
||||
*bshp = winvaddr + (bpa - busbase);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
i80312_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
/* Nothing to do. */
|
||||
}
|
||||
|
||||
int
|
||||
i80312_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
|
||||
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
|
||||
bus_addr_t *bpap, bus_space_handle_t *bshp)
|
||||
{
|
||||
|
||||
panic("i80312_io_bs_alloc(): not implemented\n");
|
||||
}
|
||||
|
||||
void
|
||||
i80312_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
panic("i80312_io_bs_free(): not implemented\n");
|
||||
}
|
||||
|
||||
void *
|
||||
i80312_io_bs_vaddr(void *t, bus_space_handle_t bsh)
|
||||
{
|
||||
|
||||
/* Not supported. */
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/* *** Routines for PCI MEM. *** */
|
||||
|
||||
int
|
||||
i80312_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
|
||||
bus_space_handle_t *bshp)
|
||||
{
|
||||
|
||||
struct i80312_softc *sc = t;
|
||||
vaddr_t va;
|
||||
uint32_t busbase, bussize;
|
||||
paddr_t pa, endpa;
|
||||
|
||||
if (bpa >= sc->sc_pmemout_base &&
|
||||
bpa < (sc->sc_pmemout_base + sc->sc_pmemout_size)) {
|
||||
busbase = sc->sc_pmemout_base;
|
||||
bussize = sc->sc_pmemout_size;
|
||||
} else if (bpa >= sc->sc_smemout_base &&
|
||||
bpa < (sc->sc_smemout_base + sc->sc_smemout_size)) {
|
||||
busbase = sc->sc_smemout_base;
|
||||
bussize = sc->sc_smemout_size;
|
||||
} else
|
||||
return (EINVAL);
|
||||
|
||||
if ((bpa + size) >= (busbase + bussize))
|
||||
return (EINVAL);
|
||||
|
||||
/*
|
||||
* Found the window -- PCI MEM space is not mapped by allocating
|
||||
* some kernel VA space and mapping the pages with pmap_enter().
|
||||
* pmap_enter() will map unmanaged pages as non-cacheable.
|
||||
*/
|
||||
pa = trunc_page(bpa - busbase);
|
||||
endpa = round_page((bpa - busbase) + size);
|
||||
|
||||
va = uvm_km_valloc(kernel_map, endpa - pa);
|
||||
if (va == 0)
|
||||
return (ENOMEM);
|
||||
|
||||
*bshp = va + (bpa & PAGE_MASK);
|
||||
|
||||
for (; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
|
||||
pmap_enter(pmap_kernel(), va, pa,
|
||||
VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED);
|
||||
}
|
||||
pmap_update(pmap_kernel());
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
i80312_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
vaddr_t va, endva;
|
||||
|
||||
va = trunc_page(bsh);
|
||||
endva = round_page(bsh + size);
|
||||
|
||||
/* Free the kernel virtual mapping. */
|
||||
uvm_km_free(kernel_map, va, endva - va);
|
||||
}
|
||||
|
||||
int
|
||||
i80312_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
|
||||
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
|
||||
bus_addr_t *bpap, bus_space_handle_t *bshp)
|
||||
{
|
||||
|
||||
panic("i80312_mem_bs_alloc(): not implemented\n");
|
||||
}
|
||||
|
||||
void
|
||||
i80312_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
|
||||
{
|
||||
|
||||
panic("i80312_mem_bs_free(): not implemented\n");
|
||||
}
|
||||
|
||||
paddr_t
|
||||
i80312_mem_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
|
||||
{
|
||||
|
||||
/* XXX */
|
||||
return (-1);
|
||||
}
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/* $NetBSD: i80312_space_asm.S,v 1.1 2001/11/09 03:27:51 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Causality Limited.
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Mark Brinicombe
|
||||
* for the NetBSD Project.
|
||||
* 4. The name of the company nor the name of the author may be used to
|
||||
* endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <machine/asm.h>
|
||||
|
||||
/*
|
||||
* bus_space functions for the i80312
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note these functions use ARM Architecture V4 instructions as
|
||||
* all i80312 based systems have Intel XScale processors on them.
|
||||
*/
|
||||
|
||||
/*
|
||||
* read single
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_r_1)
|
||||
ldrb r0, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_r_2)
|
||||
ldrh r0, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_r_4)
|
||||
ldr r0, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* write single
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_w_1)
|
||||
strb r3, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_w_2)
|
||||
strh r3, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_w_4)
|
||||
str r3, [r1, r2]
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* read multiple
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_rm_1)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_rm_1_loop:
|
||||
ldrb r3, [r0]
|
||||
strb r3, [r1], #1
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_rm_1_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_rm_2)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_rm_2_loop:
|
||||
ldrh r3, [r0]
|
||||
strh r3, [r1], #2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_rm_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_rm_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_rm_4_loop:
|
||||
ldr r3, [r0]
|
||||
str r3, [r1], #4
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_rm_4_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* write multiple
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_wm_1)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_wm_1_loop:
|
||||
ldrb r3, [r1], #1
|
||||
strb r3, [r0]
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_wm_1_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_wm_2)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_wm_2_loop:
|
||||
ldrh r3, [r1], #2
|
||||
strh r3, [r0]
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_wm_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_wm_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_wm_4_loop:
|
||||
ldr r3, [r1], #4
|
||||
str r3, [r0]
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_wm_4_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* read region
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_rr_2)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_rr_2_loop:
|
||||
ldrh r3, [r0], #2
|
||||
strh r3, [r1], #2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_rr_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_rr_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_rr_4_loop:
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r1], #4
|
||||
subs r2, r2, #1
|
||||
bne Li80312_rr_4_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* write region.
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_wr_2)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_wr_2_loop:
|
||||
ldrh r3, [r1], #2
|
||||
strh r3, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_wr_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
ENTRY(i80312_bs_wr_4)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_wr_4_loop:
|
||||
ldr r3, [r1], #4
|
||||
str r3, [r0], #4
|
||||
subs r2, r2, #1
|
||||
bne Li80312_wr_4_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* set region
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_sr_2)
|
||||
add r0, r1, r2
|
||||
mov r1, r3
|
||||
ldr r2, [sp, #0]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
Li80312_bs_sr_2_loop:
|
||||
strh r1, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_sr_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* copy region
|
||||
*/
|
||||
|
||||
ENTRY(i80312_bs_c_2)
|
||||
add r0, r1, r2
|
||||
ldr r2, [sp, #0]
|
||||
add r1, r2, r3
|
||||
ldr r2, [sp, #4]
|
||||
teq r2, #0
|
||||
moveq pc, lr
|
||||
|
||||
cmp r0, r1
|
||||
blt Li80312_bs_c_2_backwards
|
||||
|
||||
Li80312_bs_cf_2_loop:
|
||||
ldrh r3, [r0], #2
|
||||
strh r3, [r1], #2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_cf_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
||||
Li80312_bs_c_2_backwards:
|
||||
add r0, r0, r2, lsl #1
|
||||
add r1, r1, r2, lsl #1
|
||||
sub r0, r0, #2
|
||||
sub r1, r1, #2
|
||||
|
||||
Li80312_bs_cb_2_loop:
|
||||
ldrh r3, [r0], #-2
|
||||
strh r3, [r1], #-2
|
||||
subs r2, r2, #1
|
||||
bne Li80312_bs_cb_2_loop
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: i80312reg.h,v 1.6 2001/11/08 03:20:36 thorpej Exp $ */
|
||||
/* $NetBSD: i80312reg.h,v 1.7 2001/11/09 03:27:52 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2001 The NetBSD Foundation, Inc.
|
||||
|
|
@ -161,6 +161,8 @@
|
|||
#define I80312_PPB_SDER 0x5c /* Secondary Decode Enable Register */
|
||||
#define I80312_PPB_QCR 0x5e /* Queue Control Register */
|
||||
|
||||
#define PPB_SDER_PMSE (1U << 2) /* Private Memory Space Enable */
|
||||
|
||||
/*
|
||||
* Performance Monitoring Unit
|
||||
*/
|
||||
|
|
@ -228,6 +230,21 @@
|
|||
#define ATU_LIMIT(x) \
|
||||
((0xffffffffUL - ((x) - 1)) & 0xfffffff0UL)
|
||||
|
||||
#define ATU_ACR_POAE (1U << 1)
|
||||
#define ATU_ACR_SOAE (1U << 2)
|
||||
#define ATU_ACR_SDAS (1U << 7)
|
||||
#define ATU_ACR_DAE (1U << 8)
|
||||
#define ATU_ACR_PSERRIE (1U << 9)
|
||||
#define ATU_ACR_SSERRIE (1U << 10)
|
||||
#define ATU_ACR_SBMUAE (1U << 12)
|
||||
#define ATU_ACR_ADTS (1U << 15)
|
||||
#define ATU_ACR_PSERRMA (1U << 16)
|
||||
#define ATU_ACR_SSERRMA (1U << 17)
|
||||
#define ATU_ACR_DAU2GTE (1U << 18)
|
||||
#define ATU_ACR_PATUDRCA (1U << 19)
|
||||
#define ATU_ACR_SATUDRCA (1U << 20)
|
||||
#define ATU_ACR_BFN (1U << 21)
|
||||
|
||||
/*
|
||||
* Messaging Unit
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: i80312var.h,v 1.2 2001/11/05 23:38:05 thorpej Exp $ */
|
||||
/* $NetBSD: i80312var.h,v 1.3 2001/11/09 03:27:52 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Wasabi Systems, Inc.
|
||||
|
|
@ -38,7 +38,132 @@
|
|||
#ifndef _ARM_XSCALE_I80312VAR_H_
|
||||
#define _ARM_XSCALE_I80312VAR_H_
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
struct i80312_softc {
|
||||
struct device sc_dev; /* generic device glue */
|
||||
|
||||
int sc_is_host; /* indicates if we're a host or
|
||||
plugged into another host */
|
||||
|
||||
/*
|
||||
* This is the bus_space and handle used to access the
|
||||
* i80312 itself. This is filled in by the board-specific
|
||||
* front-end.
|
||||
*/
|
||||
bus_space_tag_t sc_st;
|
||||
bus_space_handle_t sc_sh;
|
||||
|
||||
/* Handles for the various subregions. */
|
||||
bus_space_handle_t sc_ppb_sh;
|
||||
bus_space_handle_t sc_atu_sh;
|
||||
|
||||
/*
|
||||
* Secondary IDSEL Select bits for providing a private
|
||||
* PCI device space.
|
||||
*/
|
||||
uint16_t sc_sisr;
|
||||
|
||||
/*
|
||||
* We expect the board-specific front-end to have already mapped
|
||||
* the PCI I/O spaces .. they're only 64K each, and I/O mappings
|
||||
* tend to be smaller than a page size, so it's generally more
|
||||
* efficient to map them all into virtual space in one fell swoop.
|
||||
*/
|
||||
vaddr_t sc_piow_vaddr; /* primary I/O window vaddr */
|
||||
vaddr_t sc_siow_vaddr; /* secondary I/O window vaddr */
|
||||
|
||||
/*
|
||||
* Variables that define the Primary Inbound window. The base
|
||||
* address is configured by a host via BAR #0. The xlate variable
|
||||
* defines the start of the local address space that it maps to.
|
||||
* The size variable defines the byte size.
|
||||
*
|
||||
* This window is used for incoming PCI memory read/write cycles
|
||||
* from a host.
|
||||
*
|
||||
* ...unless we're a host, in which case we make the Primary
|
||||
* Inbound window work like the Secondary Inbound window, so
|
||||
* that PCI devices on that bus can talk to our local RAM.
|
||||
*/
|
||||
uint32_t sc_pin_base;
|
||||
uint32_t sc_pin_xlate;
|
||||
uint32_t sc_pin_size;
|
||||
|
||||
/*
|
||||
* Variables that define the Secondary Inbound window. The
|
||||
* base variable indicates the PCI base address of the window.
|
||||
* The xlate variable defines the start of the local address
|
||||
* space that it maps to. The size variable defines the byte
|
||||
* size.
|
||||
*
|
||||
* This window is used for DMA with devices on the secondary bus.
|
||||
*/
|
||||
uint32_t sc_sin_base;
|
||||
uint32_t sc_sin_xlate;
|
||||
uint32_t sc_sin_size;
|
||||
|
||||
/*
|
||||
* This is the PCI address that the Primary Outbound Memory
|
||||
* window maps to.
|
||||
*/
|
||||
uint32_t sc_pmemout_base;
|
||||
uint32_t sc_pmemout_size;
|
||||
|
||||
/*
|
||||
* This is the PCI address that the Primary Outbound I/O
|
||||
* window maps to.
|
||||
*/
|
||||
uint32_t sc_pioout_base;
|
||||
uint32_t sc_pioout_size;
|
||||
|
||||
/*
|
||||
* This is the PCI address that the Secondary Outbound Memory
|
||||
* window maps to.
|
||||
*/
|
||||
uint32_t sc_smemout_base;
|
||||
uint32_t sc_smemout_size;
|
||||
|
||||
/*
|
||||
* This is the PCI address that the Secondary Outbound I/O
|
||||
* window maps to.
|
||||
*/
|
||||
uint32_t sc_sioout_base;
|
||||
uint32_t sc_sioout_size;
|
||||
|
||||
/*
|
||||
* This defines the private I/O and Memory spaces on the
|
||||
* Secondary bus.
|
||||
*/
|
||||
uint32_t sc_privio_base;
|
||||
uint32_t sc_privio_size;
|
||||
uint32_t sc_privmem_base;
|
||||
uint32_t sc_privmem_size;
|
||||
|
||||
uint8_t sc_sder; /* secondary decode enable register */
|
||||
|
||||
/* Bus space, DMA, and PCI tags for the PCI bus (private devices). */
|
||||
struct bus_space sc_pci_iot;
|
||||
struct bus_space sc_pci_memt;
|
||||
struct arm32_bus_dma_tag sc_pci_dmat;
|
||||
struct arm32_pci_chipset sc_pci_chipset;
|
||||
};
|
||||
|
||||
extern struct bus_space i80312_bs_tag;
|
||||
|
||||
void i80312_sdram_bounds(bus_space_tag_t, bus_space_handle_t,
|
||||
paddr_t *, psize_t *);
|
||||
|
||||
void i80312_attach(struct i80312_softc *);
|
||||
|
||||
void i80312_bs_init(bus_space_tag_t, void *);
|
||||
void i80312_io_bs_init(bus_space_tag_t, void *);
|
||||
void i80312_mem_bs_init(bus_space_tag_t, void *);
|
||||
|
||||
void i80312_pci_dma_init(bus_dma_tag_t, void *);
|
||||
|
||||
void i80312_pci_init(pci_chipset_tag_t, void *);
|
||||
|
||||
#endif /* _ARM_XSCALE_I80312VAR_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue