Fetch cache info from the Cache Type register on ARM7TDMI and "greater"
processors. Report this when the processor is attached.
This commit is contained in:
thorpej
parent
9058fce64e
commit
959181a8b2
@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.18 2001/11/26 22:26:44 thorpej Exp $ */
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/* $NetBSD: cpufunc.c,v 1.19 2001/11/29 02:24:58 thorpej Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -58,6 +58,21 @@
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#include <arm/cpufunc.h>
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/* PRIMARY CACHE VARIABLES */
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int arm_picache_size;
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int arm_picache_line_size;
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int arm_picache_ways;
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int arm_pdcache_size; /* and unified */
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int arm_pdcache_line_size;
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int arm_pdcache_ways;
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int arm_pcache_type;
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int arm_pcache_unified;
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int arm_dcache_align;
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int arm_dcache_align_mask;
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#ifdef CPU_ARM3
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struct cpu_functions arm3_cpufuncs = {
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/* CPU functions */
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@ -703,6 +718,70 @@ struct cpu_functions cpufuncs;
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u_int cputype;
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u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
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static void
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get_cachetype()
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{
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u_int ctype, isize, dsize;
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u_int multiplier;
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__asm __volatile("mrc p15, 0, %0, c0, c0, 1"
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: "=r" (ctype));
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/*
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* ...and thus spake the ARM ARM:
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*
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* If an <opcode2> value corresponding to an unimplemented or
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* reserved ID register is encountered, the System Control
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* processor returns the value of the main ID register.
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*/
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if (ctype == cpufunc_id())
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goto out;
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if ((ctype & CPU_CT_S) == 0)
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arm_pcache_unified = 1;
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/*
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* If you want to know how this code works, go read the ARM ARM.
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*/
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arm_pcache_type = CPU_CT_CTYPE(ctype);
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if (arm_pcache_unified == 0) {
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isize = CPU_CT_ISIZE(ctype);
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multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
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if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
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if (isize & CPU_CT_xSIZE_M)
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arm_picache_line_size = 0; /* not present */
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else
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arm_picache_ways = 1;
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} else {
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arm_picache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(isize) - 1);
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}
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arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
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}
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dsize = CPU_CT_DSIZE(ctype);
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multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
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if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
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if (dsize & CPU_CT_xSIZE_M)
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arm_pdcache_line_size = 0; /* not present */
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else
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arm_pdcache_ways = 0;
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} else {
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arm_pdcache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(dsize) - 1);
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}
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arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
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arm_dcache_align = arm_pdcache_line_size;
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out:
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arm_dcache_align_mask = arm_dcache_align - 1;
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}
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/*
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* Cannot panic here as we may not have a console yet ...
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*/
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@ -719,6 +798,8 @@ set_cpufuncs()
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(cputype & 0x00000f00) == 0x00000300) {
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cpufuncs = arm3_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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/* XXX Cache info? */
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arm_dcache_align_mask = -1;
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return 0;
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}
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#endif /* CPU_ARM3 */
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@ -727,6 +808,8 @@ set_cpufuncs()
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(cputype & 0x00000f00) == 0x00000600) {
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cpufuncs = arm6_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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/* XXX Cache info? */
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arm_dcache_align_mask = -1;
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return 0;
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}
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#endif /* CPU_ARM6 */
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@ -736,6 +819,8 @@ set_cpufuncs()
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(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) {
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cpufuncs = arm7_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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/* XXX Cache info? */
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arm_dcache_align_mask = -1;
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return 0;
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}
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#endif /* CPU_ARM7 */
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@ -745,6 +830,7 @@ set_cpufuncs()
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(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
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cpufuncs = arm7tdmi_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype();
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return 0;
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}
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#endif
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@ -753,6 +839,7 @@ set_cpufuncs()
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(cputype & 0x0000f000) == 0x00008000) {
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cpufuncs = arm8_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
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get_cachetype();
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return 0;
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}
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#endif /* CPU_ARM8 */
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@ -761,6 +848,7 @@ set_cpufuncs()
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pte_cache_mode = PT_C; /* Select write-through cacheing. */
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cpufuncs = arm9_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype();
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return 0;
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}
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#endif /* CPU_ARM9 */
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@ -769,6 +857,7 @@ set_cpufuncs()
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cputype == CPU_ID_SA1110) {
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cpufuncs = sa110_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
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get_cachetype();
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return 0;
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}
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#endif /* CPU_SA110 */
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@ -777,6 +866,7 @@ set_cpufuncs()
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pte_cache_mode = PT_C; /* Select write-through cacheing. */
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cpufuncs = xscale_writethrough_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype();
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return 0;
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}
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#endif /* CPU_XSCALE */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.11 2001/11/24 01:26:24 thorpej Exp $ */
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/* $NetBSD: cpu.c,v 1.12 2001/11/29 02:24:58 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe.
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@ -311,6 +311,25 @@ const struct cpu_classtab cpu_classes[] = {
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* The remaining fields in the cpu structure are filled in appropriately.
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*/
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static const char *wtnames[] = {
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"write-through",
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"write-back",
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"write-back",
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"**unknown 3**",
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"**unknown 4**",
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"write-back-locking", /* XXX XScale-specific? */
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"write-back-locking-A",
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"write-back-locking-B",
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"**unknown 8**",
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"**unknown 9**",
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"**unknown 10**",
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"**unknown 11**",
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"**unknown 12**",
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"**unknown 13**",
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"**unknown 14**",
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"**unknown 15**",
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};
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void
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identify_arm_cpu(dv, cpu_number)
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struct device *dv;
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@ -377,9 +396,29 @@ identify_arm_cpu(dv, cpu_number)
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strcat(cpu->cpu_model, " branch prediction enabled");
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/* Print the info */
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printf(": %s\n", cpu->cpu_model);
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/* Print cache info. */
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if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
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goto skip_pcache;
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if (arm_pcache_unified) {
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printf("%s: %dKB/%dB %d-way %s unified cache\n",
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dv->dv_xname, arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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} else {
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printf("%s: %dKB/%dB %d-way Instruction cache\n",
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dv->dv_xname, arm_picache_size / 1024,
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arm_picache_line_size, arm_picache_ways);
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printf("%s: %dKB/%dB %d-way %s Data cache\n",
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dv->dv_xname, arm_pdcache_size / 1024,
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arm_pdcache_line_size, arm_pdcache_ways,
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wtnames[arm_pcache_type]);
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}
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skip_pcache:
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switch (cpu->cpu_class) {
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#ifdef CPU_ARM2
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case CPU_CLASS_ARM2:
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@ -1,4 +1,4 @@
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/* $NetBSD: armreg.h,v 1.8 2001/07/18 16:31:17 rjs Exp $ */
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/* $NetBSD: armreg.h,v 1.9 2001/11/29 02:24:59 thorpej Exp $ */
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/*
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* Copyright (c) 1998, 2001 Ben Harris
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@ -224,17 +224,21 @@
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#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
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/* Cache type register definitions */
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#define CPU_CT_IINFO_MASK 0x00000fff
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#define CPU_CT_IINFO_SHIFT 0
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#define CPU_CT_DINFO_MASK 0x00fff000
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#define CPU_CT_DINFO_SHIFT 12
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#define CPU_CT_HARVARD 0x01000000
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#define CPU_CT_TYPE_MASK 0x1e000000
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/* "Info" subfields -- see ARM ARM for meanings. */
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#define CPU_CT_LINE_MASK 0x00000003
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#define CPU_CT_M_BIT 0x00000004
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#define CPU_CT_ASSOC_MASK 0x00000038
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#define CPU_CT_SIZE_MASK 0x000001c0
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#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
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#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
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#define CPU_CT_S (1U << 24) /* split cache */
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#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
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#define CPU_CT_CTYPE_WT 0 /* write-through */
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#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
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#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
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#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
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#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
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#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
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#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
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#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
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#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
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/* Fault status register definitions */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.13 2001/11/28 00:18:46 thorpej Exp $ */
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/* $NetBSD: cpufunc.h,v 1.14 2001/11/29 02:24:59 thorpej Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -396,6 +396,25 @@ int get_pc_str_offset __P((void));
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void cpu_reset __P((void)) __attribute__((__noreturn__));
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/*
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* Cache info variables.
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*/
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/* PRIMARY CACHE VARIABLES */
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int arm_picache_size;
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int arm_picache_line_size;
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int arm_picache_ways;
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int arm_pdcache_size; /* and unified */
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int arm_pdcache_line_size;
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int arm_pdcache_ways;
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int arm_pcache_type;
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int arm_pcache_unified;
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int arm_dcache_align;
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int arm_dcache_align_mask;
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#endif /* _KERNEL */
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#endif /* _ARM32_CPUFUNC_H_ */
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