Add code to run the XScale cache in write-though mode, and do so
for now...
This commit is contained in:
thorpej
parent
46f63b37c1
commit
bb706190b3
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.17 2001/11/23 19:17:04 thorpej Exp $ */
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/* $NetBSD: cpufunc.c,v 1.18 2001/11/26 22:26:44 thorpej Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -625,6 +625,74 @@ struct cpu_functions xscale_cpufuncs = {
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xscale_setup /* cpu setup */
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};
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struct cpu_functions xscale_writethrough_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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xscale_cpwait, /* cpwait */
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/* MMU functions */
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xscale_control, /* control */
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cpufunc_domains, /* domain */
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xscale_setttb, /* setttb */
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cpufunc_faultstatus, /* faultstatus */
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cpufunc_faultaddress, /* faultaddress */
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/* TLB functions */
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armv4_tlb_flushID, /* tlb_flushID */
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xscale_tlb_flushID_SE, /* tlb_flushID_SE */
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armv4_tlb_flushI, /* tlb_flushI */
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(void *)armv4_tlb_flushI, /* tlb_flushI_SE */
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache functions */
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xscale_cache_flushID, /* cache_flushID */
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(void *)xscale_cache_flushID, /* cache_flushID_SE */
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xscale_cache_flushI, /* cache_flushI */
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(void *)xscale_cache_flushI, /* cache_flushI_SE */
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xscale_cache_flushD, /* cache_flushD */
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xscale_cache_flushD_SE, /* cache_flushD_SE */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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xscale_cache_flushID, /* cache_purgeID s*/
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(void *)xscale_cache_flushID, /* cache_purgeID_E s*/
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xscale_cache_flushD, /* cache_purgeD s*/
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xscale_cache_flushD_SE, /* cache_purgeD_E s*/
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/* Other functions */
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cpufunc_nullop, /* flush_prefetchbuf */
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armv4_drain_writebuf, /* drain_writebuf */
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cpufunc_nullop, /* flush_brnchtgt_C */
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(void *)cpufunc_nullop, /* flush_brnchtgt_E */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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xscale_cache_flushI, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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xscale_cache_flushID_rng, /* cache_purgeID_rng */
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xscale_cache_flushD_rng, /* cache_purgeD_rng */
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xscale_cache_flushI_rng, /* cache_syncI_rng */
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cpufunc_null_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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xscale_context_switch, /* context_switch */
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xscale_setup /* cpu setup */
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};
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#endif /* CPU_XSCALE */
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/*
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@ -706,7 +774,8 @@ set_cpufuncs()
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#endif /* CPU_SA110 */
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#ifdef CPU_XSCALE
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if (cputype == CPU_ID_I80200) {
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cpufuncs = xscale_cpufuncs;
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pte_cache_mode = PT_C; /* Select write-through cacheing. */
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cpufuncs = xscale_writethrough_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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return 0;
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}
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc_asm_xscale.S,v 1.6 2001/11/26 18:09:08 thorpej Exp $ */
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/* $NetBSD: cpufunc_asm_xscale.S,v 1.7 2001/11/26 22:26:45 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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@ -428,6 +428,67 @@ ENTRY(xscale_cache_syncI_rng)
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mov pc, lr
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/* Used in write-through mode. */
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ENTRY(xscale_cache_flushID_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscale_cache_flushID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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/* Used in write-though mode. */
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ENTRY(xscale_cache_flushD_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscale_cache_flushD)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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/* Used in write-through mode. */
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ENTRY(xscale_cache_flushI_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscale_cache_flushI)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bpl 1b
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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/*
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* Context switch.
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*
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