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* Share a common vector page between arm26 and arm32.

Browse Source 
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
  between arm26 and arm32.
This commit is contained in:
thorpej 2001-12-20 01:20:21 +00:00
parent 2bc7fae481
commit 014157862c
47 changed files with 748 additions and 1581 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
sys/arch/acorn32/acorn32/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.1 2001/11/27 00:15:58 thorpej Exp $
# $NetBSD: genassym.cf,v 1.2 2001/12/20 01:20:21 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -44,12 +44,3 @@ define IH_NUM offsetof(struct irqhandler, ih_num)
define IH_MASKADDR offsetof(struct irqhandler, ih_maskaddr)
define IH_MASKBITS offsetof(struct irqhandler, ih_maskbits)
define IH_NEXT offsetof(struct irqhandler, ih_next)
define FH_FUNC offsetof(struct fiqhandler, fh_func)
define FH_R8 offsetof(struct fiqhandler, fh_r8)
define FH_R9 offsetof(struct fiqhandler, fh_r9)
define FH_R10 offsetof(struct fiqhandler, fh_r10)
define FH_R11 offsetof(struct fiqhandler, fh_r11)
define FH_R12 offsetof(struct fiqhandler, fh_r12)
define FH_R13 offsetof(struct fiqhandler, fh_r13)
define FH_MASK offsetof(struct fiqhandler, fh_mask)

21
sys/arch/acorn32/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.1 2001/10/05 22:27:50 reinoud Exp $ */
/* $NetBSD: irqhandler.h,v 1.2 2001/12/20 01:20:21 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -192,25 +192,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#ifdef _KERNEL
int fiq_claim __P((fiqhandler_t *));
int fiq_release __P((fiqhandler_t *));
#endif /* _KERNEL */
#endif /* _LOCORE */
#endif /* _ARM32_IRQHANDLER_H_ */
/* End of irqhandler.h */

132
sys/arch/acorn32/mainbus/fd.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: fd.c,v 1.3 2001/11/27 00:53:11 thorpej Exp $ */
/* $NetBSD: fd.c,v 1.4 2001/12/20 01:20:21 thorpej Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@ -114,13 +114,18 @@
#include <uvm/uvm_extern.h>
#include <arm/fiq.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/conf.h>
#include <machine/io.h>
#include <arm/arm32/katelib.h>
#include <machine/bus.h>
#include <arm/iomd/iomdreg.h>
#include <arm/iomd/iomdvar.h>
#include <acorn32/mainbus/piocvar.h>
#include <acorn32/mainbus/fdreg.h>
@ -156,9 +161,6 @@ enum fdc_state {
/* software state, per controller */
struct fdc_softc {
struct device sc_dev; /* boilerplate */
#ifdef NEWCONFIG
struct isadev sc_id;
#endif
void *sc_ih;
bus_space_tag_t sc_iot; /* ISA i/o space identifier */
@ -167,6 +169,9 @@ struct fdc_softc {
struct callout sc_timo_ch; /* timeout callout */
struct callout sc_intr_ch; /* pseudo-intr callout */
/* ...for pseudo-DMA... */
struct fiqhandler sc_fh; /* FIQ handler descriptor */
struct fiqregs sc_fr; /* FIQ handler reg context */
int sc_drq;
struct fd_softc *sc_fd[4]; /* pointers to children */
@ -179,9 +184,6 @@ struct fdc_softc {
/* controller driver configuration */
int fdcprobe __P((struct device *, struct cfdata *, void *));
int fdprint __P((void *, const char *));
#ifdef NEWCONFIG
void fdcforceintr __P((void *));
#endif
void fdcattach __P((struct device *, struct device *, void *));
struct cfattach fdc_ca = {
@ -259,10 +261,8 @@ struct fd_softc {
int fdprobe __P((struct device *, struct cfdata *, void *));
void fdattach __P((struct device *, struct device *, void *));
static fiqhandler_t fiqhandler;
void floppy_read_fiq __P((void));
void floppy_write_fiq __P((void));
extern char floppy_read_fiq[], floppy_read_fiq_end[];
extern char floppy_write_fiq[], floppy_write_fiq_end[];
struct cfattach fd_ca = {
sizeof(struct fd_softc), fdprobe, fdattach
@ -325,22 +325,6 @@ fdcprobe(parent, cf, aux)
out_fdc(iot, ioh, 0xdf);
out_fdc(iot, ioh, 2);
#ifdef NEWCONFIG
if (pa->pa_iobase == PIOCCF_BASE_DEFAULT || pa->pa_drq == PIOCCF_DACK_DEFAULT)
return 0;
if (pa->pa_irq == PIOCCF_IRQ_DEFAULT) {
pa->pa_irq = isa_discoverintr(fdcforceintr, aux);
if (pa->pa_irq == IRQNONE)
goto out;
/* reset it again */
bus_space_write_2(iot, ioh, fdout, 0);
delay(100);
bus_space_write_2(iot, ioh, fdout, FDO_FRST);
}
#endif
rv = 1;
pa->pa_iosize = FDC_NPORT;
@ -349,26 +333,6 @@ fdcprobe(parent, cf, aux)
return rv;
}
#ifdef NEWCONFIG
/*
* XXX This is broken, and needs fixing. In general, the interface needs
* XXX to change.
*/
void
fdcforceintr(aux)
void *aux;
{
struct isa_attach_args *ia = aux;
int iobase = ia->ia_iobase;
/* the motor is off; this should generate an error with or
without a disk drive present */
out_fdc(iot, ioh, NE7CMD_SEEK);
out_fdc(iot, ioh, 0);
out_fdc(iot, ioh, 0);
}
#endif
/*
* Arguments passed between fdcattach and fdprobe.
*/
@ -426,10 +390,6 @@ fdcattach(parent, self, aux)
callout_init(&fdc->sc_timo_ch);
callout_init(&fdc->sc_intr_ch);
#ifdef NEWCONFIG
at_setup_dmachan(fdc->sc_drq, FDC_MAXIOSIZE);
isa_establish(&fdc->sc_id, &fdc->sc_dev);
#endif
fdc->sc_ih = intr_claim(pa->pa_irq, IPL_BIO, "fdc",
fdcintr, fdc);
if (!fdc->sc_ih)
@ -1090,30 +1050,29 @@ loop:
}}
#endif
read = bp->b_flags & B_READ;
#ifdef NEWCONFIG
at_dma(read, bp->b_data + fd->sc_skip, fd->sc_nbytes,
fdc->sc_drq);
#else
/* isa_dmastart(read, bp->b_data + fd->sc_skip, fd->sc_nbytes,
fdc->sc_drq);*/
if (read)
fiqhandler.fh_func = floppy_read_fiq;
else
fiqhandler.fh_func = floppy_write_fiq;
fiqhandler.fh_r9 = IOMD_BASE + (IOMD_FIQRQ << 2);
fiqhandler.fh_r10 = fd->sc_nbytes;
fiqhandler.fh_r11 = (u_int)(bp->b_data + fd->sc_skip);
fiqhandler.fh_r12 = fdc->sc_drq;
/* fiqhandler.fh_r13 = 0;*/
fiqhandler.fh_mask = 0x01;
if (read) {
fdc->sc_fh.fh_func = floppy_read_fiq;
fdc->sc_fh.fh_size = floppy_read_fiq_end -
floppy_read_fiq;
} else {
fdc->sc_fh.fh_func = floppy_write_fiq;
fdc->sc_fh.fh_size = floppy_read_fiq_end -
floppy_read_fiq;
}
fdc->sc_fh.fh_flags = 0;
fdc->sc_fh.fh_regs = &fdc->sc_fr;
fdc->sc_fr.fr_r9 = IOMD_BASE + (IOMD_FIQRQ << 2);
fdc->sc_fr.fr_r10 = fd->sc_nbytes;
fdc->sc_fr.fr_r11 = (u_int)(bp->b_data + fd->sc_skip);
fdc->sc_fr.fr_r12 = fdc->sc_drq;
#ifdef FD_DEBUG
printf("fdc-doio:r9=%x r10=%x r11=%x r12=%x data=%x skip=%x\n", fiqhandler.fh_r9,
fiqhandler.fh_r10, fiqhandler.fh_r11,
fiqhandler.fh_r12, (u_int)bp->b_data, fd->sc_skip);
printf("fdc-doio:r9=%x r10=%x r11=%x r12=%x data=%x skip=%x\n",
fdc->sc_fr.fr_r9, fdc->sc_fr.fh_r10, fdc->sc_fr.fh_r11,
fdc->sc_fr.fh_r12, (u_int)bp->b_data, fd->sc_skip);
#endif
if (fiq_claim(&fiqhandler) == -1)
if (fiq_claim(&fdc->sc_fh) == -1)
panic("%s: Cannot claim FIQ vector\n", fdc->sc_dev.dv_xname);
#endif
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x01);
bus_space_write_2(iot, ioh, fdctl, type->rate);
#ifdef FD_DEBUG
printf("fdcintr: %s drive %d track %d head %d sec %d nblks %d\n",
@ -1180,13 +1139,8 @@ loop:
goto doio;
case IOTIMEDOUT:
#ifdef NEWCONFIG
at_dma_abort(fdc->sc_drq);
#else
/* isa_dmaabort(fdc->sc_drq);*/
if (fiq_release(&fiqhandler) == -1)
panic("%s: Cannot release FIQ vector\n", fdc->sc_dev.dv_xname);
#endif
fiq_release(&fdc->sc_fh);
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
case SEEKTIMEDOUT:
case RECALTIMEDOUT:
case RESETTIMEDOUT:
@ -1199,13 +1153,8 @@ loop:
disk_unbusy(&fd->sc_dk, (bp->b_bcount - bp->b_resid));
if (fdcresult(fdc) != 7 || (st0 & 0xf8) != 0) {
#ifdef NEWCONFIG
at_dma_abort(fdc->sc_drq);
#else
/* isa_dmaabort(fdc->sc_drq);*/
if (fiq_release(&fiqhandler) == -1)
panic("%s: Cannot release FIQ vector\n", fdc->sc_dev.dv_xname);
#endif
fiq_release(&fdc->sc_fh);
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
#ifdef FD_DEBUG
fdcstatus(&fd->sc_dev, 7, bp->b_flags & B_READ ?
"read failed" : "write failed");
@ -1215,15 +1164,8 @@ loop:
fdcretry(fdc);
goto loop;
}
#ifdef NEWCONFIG
at_dma_terminate(fdc->sc_drq);
#else
/* read = bp->b_flags & B_READ ? DMAMODE_READ : DMAMODE_WRITE;
isa_dmadone(read, bp->b_data + fd->sc_skip, fd->sc_nbytes,
fdc->sc_drq);*/
if (fiq_release(&fiqhandler) == -1)
panic("%s: Cannot release FIQ vector\n", fdc->sc_dev.dv_xname);
#endif
fiq_release(&fdc->sc_fh);
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
if (fdc->sc_errors) {
#if 0
diskerr(bp, "fd", "soft error (corrected)", LOG_PRINTF,

179
sys/arch/arm/arm/fiq.c Normal file
View File

@ -0,0 +1,179 @@
/* $NetBSD: fiq.c,v 1.1 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.1 2001/12/20 01:20:22 thorpej Exp $");
#include <sys/param.h>
#include <sys/systm.h>
#include <arm/cpufunc.h>
#include <arm/fiq.h>
TAILQ_HEAD(, fiqhandler) fiqhandler_stack =
TAILQ_HEAD_INITIALIZER(fiqhandler_stack);
extern char fiqvector[];
extern char fiq_nullhandler[], fiq_nullhandler_end[];
#ifdef __PROG32
#define IRQ_BIT I32_bit
#define FIQ_BIT F32_bit
#else
#define IRQ_BIT R15_IRQ_DISABLE
#define FIQ_BIT R15_FIQ_DISABLE
#endif /* __PROG32 */
/*
* fiq_installhandler:
*
* Actually install the FIQ handler down at the FIQ vector.
*/
static void
fiq_installhandler(void *func, size_t size)
{
#ifdef __PROG32
extern void zero_page_readwrite(void); /* XXX */
extern void zero_page_readonly(void); /* XXX */
zero_page_readwrite();
#endif
memcpy(fiqvector, func, size);
#ifdef __PROG32
zero_page_readonly();
cpu_cache_syncI_rng((vaddr_t) fiqvector, size);
#endif
}
/*
* fiq_claim:
*
* Claim the FIQ vector.
*/
int
fiq_claim(struct fiqhandler *fh)
{
struct fiqhandler *ofh;
u_int oldirqstate;
int error = 0;
if (fh->fh_size > 0x100)
return (EFBIG);
oldirqstate = disable_interrupts(FIQ_BIT);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if ((ofh->fh_flags & FH_CANPUSH) == 0) {
error = EBUSY;
goto out;
}
/* Save the previous FIQ handler's registers. */
if (ofh->fh_regs != NULL)
fiq_getregs(ofh->fh_regs);
}
/* Set FIQ mode registers to ours. */
if (fh->fh_regs != NULL)
fiq_setregs(fh->fh_regs);
TAILQ_INSERT_HEAD(&fiqhandler_stack, fh, fh_list);
/* Now copy the actual handler into place. */
fiq_installhandler(fh->fh_func, fh->fh_size);
/*
* Make sure FIQs are enabled when we return.
*
* XXX This doesn't work on arm26 -- the caller's IRQ
* XXX state is restored when we return from this function.
*/
oldirqstate &= ~FIQ_BIT;
out:
restore_interrupts(oldirqstate);
return (error);
}
/*
* fiq_release:
*
* Release the FIQ vector.
*/
void
fiq_release(struct fiqhandler *fh)
{
u_int oldirqstate;
struct fiqhandler *ofh;
oldirqstate = disable_interrupts(FIQ_BIT);
/*
* If we are the currently active FIQ handler, then we
* need to save our registers and pop the next one back
* into the vector.
*/
if (fh == TAILQ_FIRST(&fiqhandler_stack)) {
if (fh->fh_regs != NULL)
fiq_getregs(fh->fh_regs);
TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if (ofh->fh_regs != NULL)
fiq_setregs(ofh->fh_regs);
fiq_installhandler(ofh->fh_func, ofh->fh_size);
}
} else
TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list);
if (TAILQ_FIRST(&fiqhandler_stack) == NULL) {
/* Copy the NULL handler back down into the vector. */
fiq_installhandler(fiq_nullhandler,
(size_t)(fiq_nullhandler_end - fiq_nullhandler));
/*
* Make sure FIQs are disabled when we return.
*
* XXX This doesn't work on arm26 -- the caller's IRQ
* XXX state is restored when we return from this function.
*/
oldirqstate |= FIQ_BIT;
}
restore_interrupts(oldirqstate);
}

115
sys/arch/arm/arm/fiq_subr.S Normal file
View File

@ -0,0 +1,115 @@
/* $NetBSD: fiq_subr.S,v 1.1 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "assym.h"
#include "opt_cputypes.h"
#include <arm/armreg.h>
#include <arm/asm.h>
/*
* MODE_CHANGE_NOP should be inserted between a mode change and a
* banked register (R8--R15) access.
*/
#if defined(CPU_ARM2) || defined(CPU_ARM250)
#define MODE_CHANGE_NOP mov r0, r0
#else
#define MODE_CHANGE_NOP /* Data sheet says ARM3 doesn't need it */
#endif
#ifdef __PROG32
#define SWITCH_TO_FIQ_MODE \
mrs r2, cpsr_all ; \
mov r3, r2 ; \
bic r2, r2, #(PSR_MODE) ; \
orr r2, r2, #(PSR_FIQ32_MODE) ; \
msr cpsr_all, r2
#else
#define SWITCH_TO_FIQ_MODE ; \
mov r1, r15 ; \
bic r2, r1, #(R15_MODE) ; \
teqp r2, #(R15_MODE_FIQ) ; \
MODE_CHANGE_NOP
#endif /* __PROG32 */
#ifdef __PROG32
#define BACK_TO_SVC_MODE \
msr cpsr_all, r3
#else
#define BACK_TO_SVC_MODE ; \
teqp r1, #0 ; \
MODE_CHANGE_NOP
#endif /* __PROG32 */
/*
* fiq_getregs:
*
* Fetch the FIQ mode banked registers into the fiqhandler
* structure.
*/
ENTRY(fiq_getregs)
SWITCH_TO_FIQ_MODE
stmia r0, {r8-r13}
BACK_TO_SVC_MODE
mov pc, lr
/*
* fiq_setregs:
*
* Load teh FIQ mode banked registers from the fiqhandler
* structure.
*/
ENTRY(fiq_setregs)
SWITCH_TO_FIQ_MODE
ldmia r0, {r8-r13}
BACK_TO_SVC_MODE
mov pc, lr
/*
* fiq_nullhandler:
*
* Null handler copied down to the FIQ vector when the last
* FIQ handler is removed.
*/
.global _C_LABEL(fiq_nullhandler), _C_LABEL(fiq_nullhandler_end)
_C_LABEL(fiq_nullhandler):
subs pc, lr, #4
_C_LABEL(fiq_nullhandler_end):

17
sys/arch/arm/arm/undefined.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: undefined.c,v 1.11 2001/11/23 21:18:30 thorpej Exp $ */
/* $NetBSD: undefined.c,v 1.12 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@ -51,7 +51,7 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.11 2001/11/23 21:18:30 thorpej Exp $");
__KERNEL_RCSID(0, "$NetBSD: undefined.c,v 1.12 2001/12/20 01:20:22 thorpej Exp $");
#include <sys/malloc.h>
#include <sys/queue.h>
@ -301,16 +301,3 @@ undefinedinstruction(trapframe_t *frame)
userret(p);
#endif
}
void
resethandler(trapframe_t *frame)
{
#ifdef DDB
/* Extra info in case panic drops us into the debugger. */
printf("Trap frame at %p\n", frame);
#endif
panic("Branch to never-never land (zero)..... we're dead\n");
}
/* End of undefined.c */

83
sys/arch/arm/arm/vectors.S Normal file
View File

@ -0,0 +1,83 @@
/* $NetBSD: vectors.S,v 1.1 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
* Copyright (C) 1994 Brini
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of Brini may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "assym.h"
#include <machine/asm.h>
/*
* These are the exception vectors copied down to page 0.
*
* Note that FIQs are special; rather than using a level of
* indirection, we actually copy the FIQ code down into the
* vector page.
*/
.text
.align 0
.global _C_LABEL(page0), _C_LABEL(page0_end)
.global _C_LABEL(fiqvector)
_C_LABEL(page0):
ldr pc, Lreset_target
ldr pc, Lundefined_target
ldr pc, Lswi_target
ldr pc, Lprefetch_abort_target
ldr pc, Ldata_abort_target
ldr pc, Laddress_exception_target
ldr pc, Lirq_target
Lfiqvector:
.set _C_LABEL(fiqvector), . - _C_LABEL(page0)
subs pc, lr, #4
.org Lfiqvector + 0x100
Lreset_target:
.word reset_entry
Lundefined_target:
.word undefined_entry
Lswi_target:
.word swi_entry
Lprefetch_abort_target:
.word prefetch_abort_entry
Ldata_abort_target:
.word data_abort_entry
Laddress_exception_target:
.word address_exception_entry
Lirq_target:
.word irq_entry
_C_LABEL(page0_end):

179
sys/arch/arm/arm32/exception.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: exception.S,v 1.2 2001/11/28 01:06:19 thorpej Exp $ */
/* $NetBSD: exception.S,v 1.3 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@ -105,75 +105,25 @@ do_exit:
PULLFRAMEFROMSVCANDEXIT /* Restore the trap frame and exit */
/* entry point for CPU data abort */
ASENTRY_NP(data_abort_entry)
sub lr, lr, #0x00000008 /* Adjust the lr */
PUSHFRAMEINSVC /* Push trap frame and switch */
/* to SVC32 mode */
mov r0, sp /* pass the stack pointer as r0 */
add lr, pc, #exception_exit - . - 8
ldr r1, Ldata_abort_handler_address
ldr pc, [r1]
Ldata_abort_handler_address:
.word _C_LABEL(data_abort_handler_address)
.data
.global _C_LABEL(data_abort_handler_address)
_C_LABEL(data_abort_handler_address):
.word abortdata
.text
abortdata:
add r0, pc, #abortdatamsg - . - 8
b _C_LABEL(panic)
abortdatamsg:
.asciz "abortdata"
.align 0
ASENTRY_NP(prefetch_abort_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC
mov r0, sp /* pass the stack pointer as r0 */
add lr, pc, #exception_exit - . - 8
ldr r1, Lprefetch_abort_handler_address
ldr pc, [r1]
Lprefetch_abort_handler_address:
.word _C_LABEL(prefetch_abort_handler_address)
.data
.global _C_LABEL(prefetch_abort_handler_address)
_C_LABEL(prefetch_abort_handler_address):
.word abortprefetch
.text
abortprefetch:
add r0, pc, #abortprefetchmsg - . - 8
b _C_LABEL(panic)
abortprefetchmsg:
.asciz "abortprefetch"
.align 0
/*
* reset_entry:
*
* Handler for Reset exception.
*/
ASENTRY_NP(reset_entry)
adr r0, Lreset_panicmsg
mov r1, lr
bl _C_LABEL(panic)
/* NOTREACHED */
Lreset_panicmsg:
.asciz "Reset vector called, LR = 0x%08x"
.balign 4
/*
* swi_entry
*
* Main entry point for the SWI vector
* Handler for the Software Interrupt exception.
*/
ASENTRY_NP(swi_entry)
PUSHFRAME
@ -210,14 +160,103 @@ do_swi_ast:
bl _C_LABEL(ast) /* call the AST handler */
b swi_exit_loop /* Try and exit again */
/*
* prefetch_abort_entry:
*
* Handler for the Prefetch Abort exception.
*/
ASENTRY_NP(prefetch_abort_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC
mov r0, sp /* pass the stack pointer as r0 */
add lr, pc, #exception_exit - . - 8
ldr r1, Lprefetch_abort_handler_address
ldr pc, [r1]
Lprefetch_abort_handler_address:
.word _C_LABEL(prefetch_abort_handler_address)
.data
.global _C_LABEL(prefetch_abort_handler_address)
_C_LABEL(prefetch_abort_handler_address):
.word abortprefetch
.text
abortprefetch:
add r0, pc, #abortprefetchmsg - . - 8
b _C_LABEL(panic)
abortprefetchmsg:
.asciz "abortprefetch"
.align 0
/*
* We indirect the undefined vector via the handler address
* in the data area.
* Entry to the undefined handler must look like direct
* entry from the vector.
* data_abort_entry:
*
* Handler for the Data Abort exception.
*/
ASENTRY_NP(data_abort_entry)
sub lr, lr, #0x00000008 /* Adjust the lr */
PUSHFRAMEINSVC /* Push trap frame and switch */
/* to SVC32 mode */
mov r0, sp /* pass the stack pointer as r0 */
add lr, pc, #exception_exit - . - 8
ldr r1, Ldata_abort_handler_address
ldr pc, [r1]
Ldata_abort_handler_address:
.word _C_LABEL(data_abort_handler_address)
.data
.global _C_LABEL(data_abort_handler_address)
_C_LABEL(data_abort_handler_address):
.word abortdata
.text
abortdata:
add r0, pc, #abortdatamsg - . - 8
b _C_LABEL(panic)
abortdatamsg:
.asciz "abortdata"
.align 0
/*
* address_exception_entry:
*
* Handler for the Address Exception exception.
*
* NOTE: This exception isn't really used on arm32. We
* print a warning message to the console and then treat
* it like a Data Abort.
*/
ASENTRY_NP(address_exception_entry)
mrs r1, cpsr_all
mrs r2, spsr_all
mov r3, lr
adr r0, Laddress_exception_msg
bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */
b data_abort_entry
Laddress_exception_msg:
.asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
.balign 4
/*
* undefined_entry:
*
* Handler for the Undefined Instruction exception.
*
* We indirect the undefined vector via the handler address
* in the data area. Entry to the undefined handler must
* look like direct entry from the vector.
*/
ASENTRY_NP(undefined_entry)
#ifdef IPKDB
/*
@ -384,5 +423,3 @@ Lundefined_handler_indirection_data:
.global _C_LABEL(undefined_handler_address)
_C_LABEL(undefined_handler_address):
.word _C_LABEL(undefinedinstruction_bounce)
/* End of exception.S */

4
sys/arch/arm/arm32/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.7 2001/11/28 00:18:13 thorpej Exp $
# $NetBSD: genassym.cf,v 1.8 2001/12/20 01:20:22 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -44,6 +44,8 @@ include <sys/signal.h>
include <uvm/uvm_extern.h>
include <arm/fiq.h>
include <machine/pmap.h>
include <machine/frame.h>
include <machine/vmparam.h>

104
sys/arch/arm/arm32/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.1 2001/07/28 15:08:11 chris Exp $ */
/* $NetBSD: locore.S,v 1.2 2001/12/20 01:20:22 thorpej Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@ -52,6 +52,9 @@
ENTRY_NP(kernel_text)
#endif
.text
.align 0
ASENTRY_NP(start)
add r1, pc, #(Lstart - . - 8)
ldmia r1, {r1, r2, sp} /* Set initial stack and */
@ -99,73 +102,8 @@ Lstart:
svcstk:
.space INIT_ARM_STACK_SIZE
/*
* Instructions to copy to the bottom of zero page
* These are the entry point to the system exception routines
*/
.text
.align 0
.global _C_LABEL(page0), _C_LABEL(page0_end)
_C_LABEL(page0):
ldr pc, [pc, #Lreset - . - 8]
ldr pc, [pc, #Lundefined - . - 8]
ldr pc, [pc, #Lswi - . - 8]
ldr pc, [pc, #Labortpre - . - 8]
ldr pc, [pc, #Labortdata - . - 8]
ldr pc, [pc, #Laddrexc - . - 8]
ldr pc, [pc, #Lirq - . - 8]
ldr pc, [pc, #Lfiq - . - 8]
Lreset:
.word reset_entry
Lundefined:
.word undefined_entry
Lswi:
.word swi_entry
Labortpre:
.word prefetch_abort_entry
Labortdata:
.word data_abort_entry
Laddrexc:
.word addrexc
Lirq:
.word irq_entry
Lfiq:
.word fiq
_C_LABEL(page0_end) = .
/* vector 0x00000000 - RESET */
ASENTRY_NP(reset_entry)
PUSHFRAME
mov r0, sp /* Pass the frame to function */
b _C_LABEL(resethandler) /* It's a branch throught zero ! */
/* vector 0x00000008 - ADDRESS EXCEPTION */
ASENTRY_NP(addrexc)
mrs r1, cpsr_all
mrs r2, spsr_all
mov r3, lr
add r0, pc, #Laddrexcmsg - . - 8
bl _C_LABEL(printf)
b data_abort_entry
Laddrexcmsg:
.asciz "address exception CPSR=%08x SPSR=%08x lr=%08x\n"
.align 0
/* vector 0x0000001C - FIQ */
ASENTRY_NP(fiq)
ldr r0, Lfiqmsg
b _C_LABEL(panic)
Lfiqmsg:
.asciz "fiq"
.align 0
#ifndef OFW
/* OFW based systems will used OF_boot() */
@ -227,40 +165,6 @@ Lcpu_reset_needs_v4_MMU_disable:
#endif /* OFW */
#ifdef IPKDB
#if 0
/*
* ipkdbfbyte and ipkdbsbyte are now in ipkdb_glue.c and do not tweak
* the abort handler anymore
*/
ENTRY_NP(ipkdbfbyte)
ldr ip, abortp
ldr r2, [ip]
add r3, pc, #ipkdbfault - . - 8
str r3, [ip]
ldrb r0, [r0]
str r2, [ip]
mov pc, lr
ENTRY_NP(ipkdbsbyte)
ldr ip, abortp
ldr r2, [ip]
add r3, pc, #ipkdbfault - . - 8
str r3, [ip]
strb r1, [r0]
sub r0, r0, r0
str r2, [ip]
mov pc, lr
abortp:
.word Labortdata - _C_LABEL(page0)
ipkdbfault:
mov r0, #0xd3
msr cpsr_all, r0
mvn r0, #0 /* mov r0, #-1 */
str r2, [ip]
mov pc, lr
#endif
/*
* Execute(inst, psr, args, sp)
*

6
sys/arch/arm/conf/files.arm
View File

@ -1,4 +1,4 @@
# $NetBSD: files.arm,v 1.46 2001/11/28 10:21:12 lukem Exp $
# $NetBSD: files.arm,v 1.47 2001/12/20 01:20:23 thorpej Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@ -31,6 +31,9 @@ file arch/arm/arm32/db_interface.c ddb & arm32
file arch/arm/arm/db_trace.c ddb
file arch/arm/arm32/db_machdep.c ddb & arm32
# FIQ support
file arch/arm/arm/fiq.c
file arch/arm/arm/fiq_subr.S
# mainbus files
device mainbus { [base = -1], [dack = -1], [irq = -1] }
@ -67,6 +70,7 @@ file arch/arm/arm/procfs_machdep.c procfs
file arch/arm/arm/sig_machdep.c
file arch/arm/arm/sigcode.S
file arch/arm/arm/undefined.c
file arch/arm/arm/vectors.S
file arch/arm/arm/vm_machdep_arm.c
# files common to arm32 implementations

11
sys/arch/arm/footbridge/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.1 2001/11/27 00:15:58 thorpej Exp $
# $NetBSD: genassym.cf,v 1.2 2001/12/20 01:20:23 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -44,12 +44,3 @@ define IH_NUM offsetof(struct irqhandler, ih_num)
define IH_MASKADDR offsetof(struct irqhandler, ih_maskaddr)
define IH_MASKBITS offsetof(struct irqhandler, ih_maskbits)
define IH_NEXT offsetof(struct irqhandler, ih_next)
define FH_FUNC offsetof(struct fiqhandler, fh_func)
define FH_R8 offsetof(struct fiqhandler, fh_r8)
define FH_R9 offsetof(struct fiqhandler, fh_r9)
define FH_R10 offsetof(struct fiqhandler, fh_r10)
define FH_R11 offsetof(struct fiqhandler, fh_r11)
define FH_R12 offsetof(struct fiqhandler, fh_r12)
define FH_R13 offsetof(struct fiqhandler, fh_r13)
define FH_MASK offsetof(struct fiqhandler, fh_mask)

36
sys/arch/arm/include/cpufunc.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpufunc.h,v 1.14 2001/11/29 02:24:59 thorpej Exp $ */
/* $NetBSD: cpufunc.h,v 1.15 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@ -358,23 +358,37 @@ void xscale_setup __P((char *string));
/*
* Macros for manipulating CPU interrupts
*/
#define disable_interrupts(mask) \
#ifdef __PROG32
#define disable_interrupts(mask) \
(SetCPSR((mask) & (I32_bit | F32_bit), (mask) & (I32_bit | F32_bit)))
#define enable_interrupts(mask) \
#define enable_interrupts(mask) \
(SetCPSR((mask) & (I32_bit | F32_bit), 0))
#define restore_interrupts(old_cpsr) \
#define restore_interrupts(old_cpsr) \
(SetCPSR((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
#else /* ! __PROG32 */
#define disable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
/*
* Functions to manipulate the CPSR
* (in arm/arm32/setcpsr.S)
*/
#define enable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
u_int SetCPSR __P((u_int bic, u_int eor));
u_int GetCPSR __P((void));
#define restore_interrupts(old_r15) \
(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
#endif /* __PROG32 */
#ifdef __PROG32
/* Functions to manipulate the CPSR. */
u_int SetCPSR(u_int bic, u_int eor);
u_int GetCPSR(void);
#else
/* Functions to manipulate the processor control bits in r15. */
u_int set_r15(u_int bic, u_int eor);
u_int get_r15(void);
#endif /* __PROG32 */
/*
* Functions to manipulate cpu r13

68
sys/arch/arm/include/fiq.h Normal file
View File

@ -0,0 +1,68 @@
/* $NetBSD: fiq.h,v 1.1 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_FIQ_H_
#define _ARM_FIQ_H_
#include <sys/queue.h>
struct fiqregs {
u_int fr_r8; /* FIQ mode r8 */
u_int fr_r9; /* FIQ mode r9 */
u_int fr_r10; /* FIQ mode r10 */
u_int fr_r11; /* FIQ mode r11 */
u_int fr_r12; /* FIQ mode r12 */
u_int fr_r13; /* FIQ mode r13 */
};
struct fiqhandler {
TAILQ_ENTRY(fiqhandler) fh_list;/* link in the FIQ handler stack */
void *fh_func; /* FIQ handler routine */
size_t fh_size; /* size of FIQ handler */
int fh_flags; /* flags; see below */
struct fiqregs *fh_regs; /* pointer to regs structure */
};
#define FH_CANPUSH 0x01 /* can push this handler out of the way */
int fiq_claim(struct fiqhandler *);
void fiq_release(struct fiqhandler *);
void fiq_getregs(struct fiqregs *);
void fiq_setregs(struct fiqregs *);
#endif /* _ARM_FIQ_H_ */

3
sys/arch/arm/include/undefined.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: undefined.h,v 1.3 2001/11/16 13:12:06 bjh21 Exp $ */
/* $NetBSD: undefined.h,v 1.4 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 1995-1996 Mark Brinicombe.
@ -80,7 +80,6 @@ void install_coproc_handler_static __P((int, struct undefined_handler *));
/* Calls up to undefined.c from trap handlers */
void undefinedinstruction(struct trapframe *);
void resethandler(struct trapframe *);
#endif

4
sys/arch/arm/iomd/iomd_fiq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: iomd_fiq.S,v 1.1 2001/10/05 22:27:40 reinoud Exp $ */
/* $NetBSD: iomd_fiq.S,v 1.2 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -109,5 +109,3 @@ ENTRY_NP(floppy_write_fiq)
.global _C_LABEL(floppy_write_fiq_end)
_C_LABEL(floppy_write_fiq_end):
/* End of fiq.S */

44
sys/arch/arm/iomd/iomd_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: iomd_irq.S,v 1.1 2001/10/05 22:27:41 reinoud Exp $ */
/* $NetBSD: iomd_irq.S,v 1.2 2001/12/20 01:20:23 thorpej Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -560,45 +560,3 @@ _C_LABEL(intrcnt):
.long 0
_C_LABEL(eintrcnt):
#endif /* IRQSTATS */
/* FIQ code */
ENTRY(fiq_setregs) /* Sets up the FIQ handler */
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
ldr r9, [r0, #FH_R9]
ldr r10, [r0, #FH_R10]
ldr r11, [r0, #FH_R11]
ldr r12, [r0, #FH_R12]
ldr r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
ENTRY(fiq_getregs) /* Gets the FIQ registers */
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
str r8, [r0, #FH_R8] /* Update FIQ registers*/
str r9, [r0, #FH_R9]
str r10, [r0, #FH_R10]
str r11, [r0, #FH_R11]
str r12, [r0, #FH_R12]
str r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
/* End of irq.S */

80
sys/arch/arm/iomd/iomd_irqhandler.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: iomd_irqhandler.c,v 1.3 2001/11/27 01:03:53 thorpej Exp $ */
/* $NetBSD: iomd_irqhandler.c,v 1.4 2001/12/20 01:20:24 thorpej Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -55,7 +55,6 @@
#include <arm/arm32/katelib.h>
irqhandler_t *irqhandlers[NIRQS];
fiqhandler_t *fiqhandlers;
int current_intr_depth;
u_int current_mask;
@ -73,8 +72,6 @@ extern char *_intrnames;
extern void zero_page_readonly __P((void));
extern void zero_page_readwrite __P((void));
extern int fiq_setregs __P((fiqhandler_t *));
extern int fiq_getregs __P((fiqhandler_t *));
extern void set_spl_masks __P((void));
/*
@ -94,9 +91,6 @@ irq_init()
irqblock[loop] = 0;
}
/* Clear the FIQ handler */
fiqhandlers = NULL;
/* Clear the IRQ/FIQ masks in the IOMD */
IOMD_WRITE_BYTE(IOMD_IRQMSKA, 0x00);
IOMD_WRITE_BYTE(IOMD_IRQMSKB, 0x00);
@ -544,75 +538,3 @@ stray_irqhandler(mask)
log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
stray_irqs >= 8 ? ": stopped logging" : "");
}
/*
* int fiq_claim(fiqhandler_t *handler)
*
* Claim FIQ's and install a handler for them.
*/
int
fiq_claim(handler)
fiqhandler_t *handler;
{
/* Fail if the FIQ's are already claimed */
if (fiqhandlers)
return(-1);
if (handler->fh_size > 0xc0)
return(-1);
/* Install the handler */
fiqhandlers = handler;
/* Now we have to actually install the FIQ handler */
/* Eventually we will copy this down but for the moment ... */
zero_page_readwrite();
WriteWord(0x0000003c, (u_int) handler->fh_func);
zero_page_readonly();
/* We must now set up the FIQ registers */
fiq_setregs(handler);
/* Set up the FIQ mask */
IOMD_WRITE_BYTE(IOMD_FIQMSK, handler->fh_mask);
/* Make sure that the FIQ's are enabled */
enable_interrupts(F32_bit);
return(0);
}
/*
* int fiq_release(fiqhandler_t *handler)
*
* Release FIQ's and remove a handler for them.
*/
int
fiq_release(handler)
fiqhandler_t *handler;
{
/* Fail if the handler is wrong */
if (fiqhandlers != handler)
return(-1);
/* Disable FIQ interrupts */
disable_interrupts(F32_bit);
/* Clear up the FIQ mask */
IOMD_WRITE_BYTE(IOMD_FIQMSK, 0x00);
/* Retrieve the FIQ registers */
fiq_getregs(handler);
/* Remove the handler */
fiqhandlers = NULL;
return(0);
}
/* End of irqhandler.c */

77
sys/arch/arm26/arm26/fiq.c
View File

@ -1,77 +0,0 @@
/* $NetBSD: fiq.c,v 1.3 2001/09/10 23:17:48 bjh21 Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.3 2001/09/10 23:17:48 bjh21 Exp $");
#include <sys/systm.h>
#include <machine/fiq.h>
int fiq_claimed;
extern char fiqhandler[];
void (*fiq_downgrade_handler)(void);
int
fiq_claim(void *handler, size_t size)
{
int s;
if (size > 0x100)
return -1;
s = splhigh();
if (fiq_claimed) {
splx(s);
return -1;
}
fiq_claimed = 1;
splx(s);
fiq_installhandler(handler, size);
return 0;
}
void
fiq_installhandler(void *handler, size_t size)
{
memcpy(fiqhandler, handler, size);
}
void
fiq_release()
{
KASSERT(fiq_claimed);
fiq_claimed = 0;
}

5
sys/arch/arm26/arm26/irq.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: irq.c,v 1.24 2001/11/29 22:17:17 bjh21 Exp $ */
/* $NetBSD: irq.c,v 1.25 2001/12/20 01:20:24 thorpej Exp $ */
/*-
* Copyright (c) 2000, 2001 Ben Harris
@ -33,7 +33,7 @@
#include <sys/param.h>
__RCSID("$NetBSD: irq.c,v 1.24 2001/11/29 22:17:17 bjh21 Exp $");
__RCSID("$NetBSD: irq.c,v 1.25 2001/12/20 01:20:24 thorpej Exp $");
#include <sys/device.h>
#include <sys/kernel.h> /* for cold */
@ -78,6 +78,7 @@ extern char *irqnames[];
int current_intr_depth = 0;
#if NFIQ > 0
void (*fiq_downgrade_handler)(void);
int fiq_want_downgrade;
#endif

79
sys/arch/arm26/arm26/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.20 2001/12/01 17:30:07 bjh21 Exp $ */
/* $NetBSD: locore.S,v 1.21 2001/12/20 01:20:24 thorpej Exp $ */
/*
* Copyright (c) 1998, 1999, 2000 Ben Harris
* Copyright (C) 1994-1997 Mark Brinicombe
@ -116,39 +116,6 @@ _C_LABEL(kernel_text):
* FIQ
*/
.global _C_LABEL(page0), _C_LABEL(page0_end)
_C_LABEL(page0):
ldr pc, Lreset_target
ldr pc, Lundefined_target
ldr pc, Lswi_target
ldr pc, Lprefetch_abort_target
ldr pc, Ldata_abort_target
ldr pc, Laddress_exception_target
ldr pc, Lirq_target
Lfiqhandler:
.global _C_LABEL(fiqhandler)
.set _C_LABEL(fiqhandler), . - _C_LABEL(page0)
subs pc, lr, #4
#if NFIQ > 0
.org Lfiqhandler + 0x100
#endif
Lreset_target:
.word reset_entry
Lundefined_target:
.word undefined_entry
Lswi_target:
.word swi_entry
Lprefetch_abort_target:
.word prefetch_abort_entry
Ldata_abort_target:
.word data_abort_entry
Laddress_exception_target:
.word address_exception_entry
Lirq_target:
.word irq_entry
_C_LABEL(page0_end):
/*
* Trap handlers
*
@ -377,31 +344,7 @@ ENTRY(set_r13_irq)
teqp r15, #(R15_IRQ_DISABLE | R15_MODE_SVC)
MODE_CHANGE_NOP
movs r15, lr
#if NFIQ > 0
/* LINTSTUB: Func: void fiq_setregs(const struct fiq_regs *) */
ENTRY(fiq_setregs)
/* We assume that there's no need to disable FIQs while we work. */
mov r1, r15
bic r2, r1, #R15_MODE
teqp r2, #R15_MODE_FIQ
MODE_CHANGE_NOP
ldmia r0, {r8-r13}
teqp r1, #0
MODE_CHANGE_NOP
mov r15, lr
/* LINTSTUB: Func: void fiq_getregs(struct fiq_regs *) */
ENTRY(fiq_getregs)
mov r1, r15
bic r2, r1, #R15_MODE
teqp r2, #R15_MODE_FIQ
MODE_CHANGE_NOP
stmia r0, {r8-r13}
teqp r1, #0
MODE_CHANGE_NOP
mov r15, lr
#endif
/*
* These are grotty, and very non-APCS. The CPU interrupt status
* is part of the state that's restored on function exit, so the
@ -429,6 +372,22 @@ ENTRY(fiq_off)
/* LINTSTUB: Func: void fiq_on(void) */
ENTRY(fiq_on)
bics r15, r14, #(R15_FIQ_DISABLE)
/*
* These are grotty, and very non-APCS. The CPU interrupt status
* is part of the state that's restored on function exit, so the
* effect of these only persists until then.
*/
ENTRY_NP(set_r15)
mov r3, r14 /* get caller's IRQ state */
bic r2, r3, r0
eor r2, r2, r1
mov r0, r3 /* return old IRQ state */
movs r15, r3
ENTRY_NP(get_r15)
mov r0, r14
movs r15, lr
/*
* Low-level context-switch operation. cpu_switch() is in C -- this
@ -504,4 +463,4 @@ _C_LABEL(intrcnt):
.global _C_LABEL(eintrcnt)
_C_LABEL(eintrcnt):
RCSID("$NetBSD: locore.S,v 1.20 2001/12/01 17:30:07 bjh21 Exp $")
RCSID("$NetBSD: locore.S,v 1.21 2001/12/20 01:20:24 thorpej Exp $")

5
sys/arch/arm26/conf/files.arm26
View File

@ -1,4 +1,4 @@
# $NetBSD: files.arm26,v 1.42 2001/11/29 22:17:16 bjh21 Exp $
# $NetBSD: files.arm26,v 1.43 2001/12/20 01:20:24 thorpej Exp $
# Copyright (c) 1997, 1998, 2000 Ben Harris
# All rights reserved.
@ -68,6 +68,7 @@ file arch/arm26/iobus/iobus.c iobus
device ioc { [bank = -1], [offset = 0] }
attach ioc at iobus
file arch/arm26/iobus/ioc.c ioc needs-flag
file arch/arm26/ioc/ioc_fiq_util.S fiq needs-flag
# I^2C bus (bit-banged through IOC control register)
device iic { addr = -1 }
@ -208,8 +209,6 @@ file arch/arm26/arm26/conf.c
file arch/arm26/arm26/cons_machdep.c
file arch/arm26/arm26/copyinout.S
file arch/arm26/arm26/except.c
file arch/arm26/arm26/fiq.c fiq needs-flag
file arch/arm26/arm26/fiq_util.S fiq
file arch/arm26/arm26/irq.c
file arch/arm26/arm26/Locore.c
file arch/arm26/arm26/machdep.c

16
sys/arch/arm26/include/fiq.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: fiq.h,v 1.3 2001/09/10 23:17:49 bjh21 Exp $ */
/* $NetBSD: fiq.h,v 1.4 2001/12/20 01:20:25 thorpej Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
@ -45,20 +45,6 @@
#define FIQ_FDDRQ IOC_FIQ_FH0 /* Floppy disc data request */
#define FIQ_SINTR IOC_FIQ_C4 /* Serial line interrupt */
struct fiq_regs {
register_t r8_fiq;
register_t r9_fiq;
register_t r10_fiq;
register_t r11_fiq;
register_t r12_fiq;
register_t r13_fiq;
};
extern int fiq_claim(void *, size_t);
extern void fiq_release(void);
extern void fiq_installhandler(void *, size_t);
extern void fiq_setregs(const struct fiq_regs *);
extern void fiq_getregs(struct fiq_regs *);
extern void (*fiq_downgrade_handler)(void);
#endif

43
sys/arch/arm26/ioc/if_eca.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_eca.c,v 1.10 2001/11/07 19:53:19 bjh21 Exp $ */
/* $NetBSD: if_eca.c,v 1.11 2001/12/20 01:20:25 thorpej Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
@ -29,7 +29,7 @@
#include <sys/param.h>
__KERNEL_RCSID(0, "$NetBSD: if_eca.c,v 1.10 2001/11/07 19:53:19 bjh21 Exp $");
__KERNEL_RCSID(0, "$NetBSD: if_eca.c,v 1.11 2001/12/20 01:20:25 thorpej Exp $");
#include <sys/device.h>
#include <sys/malloc.h>
@ -132,6 +132,11 @@ eca_attach(struct device *parent, struct device *self, void *aux)
if_attach(ifp);
eco_ifattach(ifp, myaddr);
sc->sc_fiqhandler.fh_func = eca_fiqhandler;
sc->sc_fiqhandler.fh_size = eca_efiqhandler - eca_fiqhandler;
sc->sc_fiqhandler.fh_flags = 0;
sc->sc_fiqhandler.fh_regs = &sc->sc_fiqstate.efs_rx_fiqregs;
printf("\n");
}
@ -148,8 +153,8 @@ eca_init(struct ifnet *ifp)
return err;
/* Claim the FIQ early, in case we don't get it. */
if (fiq_claim(eca_fiqhandler, eca_efiqhandler - eca_fiqhandler))
return EBUSY;
if ((err = fiq_claim(&sc->sc_fiqhandler)) != 0)
return err;
if (sc->sc_rcvmbuf == NULL) {
err = eca_init_rxbuf(sc, M_WAIT);
@ -219,7 +224,7 @@ eca_txframe(struct ifnet *ifp, struct mbuf *m)
struct eca_softc *sc = ifp->if_softc;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct fiq_regs fr;
struct fiqregs fr;
ioc_fiq_setmask(0);
/* Start flag-filling while we work out what to do next. */
@ -228,10 +233,10 @@ eca_txframe(struct ifnet *ifp, struct mbuf *m)
sc->sc_fiqstate.efs_fiqhandler = eca_fiqhandler_tx;
sc->sc_transmitting = 1;
sc->sc_txmbuf = m;
fr.r8_fiq = (register_t)sc->sc_ioh.a1;
fr.r9_fiq = (register_t)sc->sc_txmbuf->m_data;
fr.r10_fiq = (register_t)sc->sc_txmbuf->m_len;
fr.r11_fiq = (register_t)&sc->sc_fiqstate;
fr.fr_r8 = (register_t)sc->sc_ioh.a1;
fr.fr_r9 = (register_t)sc->sc_txmbuf->m_data;
fr.fr_r10 = (register_t)sc->sc_txmbuf->m_len;
fr.fr_r11 = (register_t)&sc->sc_fiqstate;
fiq_setregs(&fr);
sc->sc_fiqstate.efs_tx_curmbuf = sc->sc_txmbuf;
fiq_downgrade_handler = eca_tx_downgrade;
@ -351,13 +356,13 @@ void
eca_init_rx_soft(struct eca_softc *sc)
{
struct ifnet *ifp = &sc->sc_ec.ec_if;
struct fiq_regs *fr = &sc->sc_fiqstate.efs_rx_fiqregs;
struct fiqregs *fr = &sc->sc_fiqstate.efs_rx_fiqregs;
memset(fr, 0, sizeof(*fr));
fr->r8_fiq = (register_t)sc->sc_ioh.a1;
fr->r9_fiq = (register_t)sc->sc_rcvmbuf->m_data;
fr->r10_fiq = (register_t)ECO_ADDR_LEN;
fr->r11_fiq = (register_t)&sc->sc_fiqstate;
fr->fr_r8 = (register_t)sc->sc_ioh.a1;
fr->fr_r9 = (register_t)sc->sc_rcvmbuf->m_data;
fr->fr_r10 = (register_t)ECO_ADDR_LEN;
fr->fr_r11 = (register_t)&sc->sc_fiqstate;
sc->sc_fiqstate.efs_rx_curmbuf = sc->sc_rcvmbuf;
sc->sc_fiqstate.efs_rx_flags = 0;
sc->sc_fiqstate.efs_rx_myaddr = LLADDR(ifp->if_sadl)[0];
@ -375,7 +380,7 @@ eca_init_rx_hard(struct eca_softc *sc)
{
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct fiq_regs *fr = &sc->sc_fiqstate.efs_rx_fiqregs;
struct fiqregs *fr = &sc->sc_fiqstate.efs_rx_fiqregs;
sc->sc_fiqstate.efs_fiqhandler = eca_fiqhandler_rx;
sc->sc_transmitting = 0;
@ -417,7 +422,7 @@ eca_stop(struct ifnet *ifp, int disable)
ioc_fiq_setmask(0);
fiq_downgrade_handler = NULL;
eca_fiqowner = NULL;
fiq_release();
fiq_release(&sc->sc_fiqhandler);
if (sc->sc_rcvmbuf != NULL) {
m_freem(sc->sc_rcvmbuf);
sc->sc_rcvmbuf = NULL;
@ -449,7 +454,7 @@ eca_gotframe(void *arg)
struct ifnet *ifp = &sc->sc_ec.ec_if;
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh = sc->sc_ioh;
struct fiq_regs fr;
struct fiqregs fr;
int sr2;
struct mbuf *m, *mtail, *n, *reply;
@ -469,7 +474,7 @@ eca_gotframe(void *arg)
if (eca_init_rxbuf(sc, M_DONTWAIT) == 0) {
ifp->if_ipackets++; /* XXX packet vs frame? */
/* Trim the tail of the mbuf chain. */
mtail->m_len = (caddr_t)(fr.r9_fiq) - mtail->m_data;
mtail->m_len = (caddr_t)(fr.fr_r9) - mtail->m_data;
m_freem(mtail->m_next);
mtail->m_next = NULL;
/* Set up the header of the chain. */
@ -488,7 +493,7 @@ eca_gotframe(void *arg)
mtail = sc->sc_fiqstate.efs_rx_curmbuf;
log(LOG_ERR, "%s: Rx overrun (state = %d, len = %ld)\n",
sc->sc_dev.dv_xname, sc->sc_ec.ec_state,
(caddr_t)(fr.r9_fiq) - mtail->m_data);
(caddr_t)(fr.fr_r9) - mtail->m_data);
ifp->if_ierrors++;
/* Discard the rest of the frame. */

7
sys/arch/arm26/ioc/if_ecavar.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: if_ecavar.h,v 1.3 2001/09/20 21:54:11 bjh21 Exp $ */
/* $NetBSD: if_ecavar.h,v 1.4 2001/12/20 01:20:25 thorpej Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
@ -37,13 +37,15 @@
#include <net/if.h>
#include <net/if_eco.h>
#include <arm/fiq.h>
#include <machine/bus.h>
#include <machine/fiq.h>
struct eca_fiqstate {
void *efs_fiqhandler;
struct mbuf *efs_rx_curmbuf;
struct fiq_regs efs_rx_fiqregs;
struct fiqregs efs_rx_fiqregs;
u_int32_t efs_rx_flags;
u_int8_t efs_rx_myaddr;
struct mbuf *efs_tx_curmbuf;
@ -59,6 +61,7 @@ struct eca_softc {
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
void *sc_rx_soft;
struct fiqhandler sc_fiqhandler;
struct eca_fiqstate sc_fiqstate;
struct mbuf *sc_rcvmbuf;
struct mbuf *sc_txmbuf;

4
sys/arch/arm26/arm26/fiq_util.S → sys/arch/arm26/ioc/ioc_fiq_util.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: fiq_util.S,v 1.3 2001/09/22 17:16:18 bjh21 Exp $ */
/* $NetBSD: ioc_fiq_util.S,v 1.1 2001/12/20 01:20:25 thorpej Exp $ */
/*-
* Copyright (c) 2001 Ben Harris
@ -29,7 +29,7 @@
#include <machine/asm.h>
RCSID("$NetBSD: fiq_util.S,v 1.3 2001/09/22 17:16:18 bjh21 Exp $")
RCSID("$NetBSD: ioc_fiq_util.S,v 1.1 2001/12/20 01:20:25 thorpej Exp $")
#include <machine/memcreg.h>
#include <arch/arm26/iobus/iocreg.h>

11
sys/arch/arm32/arm32/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.10 2001/11/27 00:15:58 thorpej Exp $
# $NetBSD: genassym.cf,v 1.11 2001/12/20 01:20:25 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -44,12 +44,3 @@ define IH_NUM offsetof(struct irqhandler, ih_num)
define IH_MASKADDR offsetof(struct irqhandler, ih_maskaddr)
define IH_MASKBITS offsetof(struct irqhandler, ih_maskbits)
define IH_NEXT offsetof(struct irqhandler, ih_next)
define FH_FUNC offsetof(struct fiqhandler, fh_func)
define FH_R8 offsetof(struct fiqhandler, fh_r8)
define FH_R9 offsetof(struct fiqhandler, fh_r9)
define FH_R10 offsetof(struct fiqhandler, fh_r10)
define FH_R11 offsetof(struct fiqhandler, fh_r11)
define FH_R12 offsetof(struct fiqhandler, fh_r12)
define FH_R13 offsetof(struct fiqhandler, fh_r13)
define FH_MASK offsetof(struct fiqhandler, fh_mask)

4
sys/arch/arm32/conf/files.arm32
View File

@ -1,4 +1,4 @@
# $NetBSD: files.arm32,v 1.132 2001/11/28 10:21:12 lukem Exp $
# $NetBSD: files.arm32,v 1.133 2001/12/20 01:20:25 thorpej Exp $
#
# First try for arm-specific configuration info
#
@ -125,7 +125,7 @@ file arch/arm/arm32/spl.S
# Shark specific files
file arch/arm32/shark/shark_machdep.c shark
file arch/arm32/shark/sequoia.c shark
file arch/arm32/shark/fiq.S shark
file arch/arm32/shark/shark_fiq.S shark
file arch/arm32/shark/hat.c shark
file arch/arm32/isa/isa_irqhandler.c shark
file arch/arm32/isa/clock.c shark

21
sys/arch/arm32/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.22 2001/12/06 11:54:07 bjh21 Exp $ */
/* $NetBSD: irqhandler.h,v 1.23 2001/12/20 01:20:26 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -151,25 +151,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#ifdef _KERNEL
int fiq_claim __P((fiqhandler_t *));
int fiq_release __P((fiqhandler_t *));
#endif /* _KERNEL */
#endif /* _LOCORE */
#endif /* _ARM32_IRQHANDLER_H_ */
/* End of irqhandler.h */

44
sys/arch/arm32/isa/isa_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: isa_irq.S,v 1.7 1999/10/26 06:53:43 cgd Exp $ */
/* $NetBSD: isa_irq.S,v 1.8 2001/12/20 01:20:26 thorpej Exp $ */
/*
* Copyright 1997
@ -550,45 +550,3 @@ _C_LABEL(intrcnt):
.long 0
_C_LABEL(eintrcnt):
#endif /* IRQSTATS */
/* FIQ code */
ENTRY(fiq_setregs)
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
orr r2, r2, #(I32_bit | F32_bit) /* IRQs/FIQs definitely off */
msr cpsr_all, r2
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
ldr r9, [r0, #FH_R9]
ldr r10, [r0, #FH_R10]
ldr r11, [r0, #FH_R11]
ldr r12, [r0, #FH_R12]
ldr r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
ENTRY(fiq_getregs)
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
orr r2, r2, #(I32_bit | F32_bit) /* IRQs/FIQs definitely off */
msr cpsr_all, r2
str r8, [r0, #FH_R8] /* Update FIQ registers*/
str r9, [r0, #FH_R9]
str r10, [r0, #FH_R10]
str r11, [r0, #FH_R11]
str r12, [r0, #FH_R12]
str r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
/* End of irq.S */

76
sys/arch/arm32/isa/isa_irqhandler.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: isa_irqhandler.c,v 1.8 2001/11/27 01:06:28 thorpej Exp $ */
/* $NetBSD: isa_irqhandler.c,v 1.9 2001/12/20 01:20:26 thorpej Exp $ */
/*
* Copyright 1997
@ -87,7 +87,6 @@
#include <machine/cpu.h>
irqhandler_t *irqhandlers[NIRQS];
fiqhandler_t *fiqhandlers;
int current_intr_depth;
u_int current_mask;
@ -105,8 +104,6 @@ extern char *_intrnames;
extern void zero_page_readonly __P((void));
extern void zero_page_readwrite __P((void));
extern int fiq_setregs __P((fiqhandler_t *));
extern int fiq_getregs __P((fiqhandler_t *));
extern void set_spl_masks __P((void));
void irq_calculatemasks __P((void));
@ -130,9 +127,6 @@ irq_init()
irqblock[loop] = 0;
}
/* Clear the FIQ handler */
fiqhandlers = NULL;
/*
* Setup the irqmasks for the different Interrupt Priority Levels
* We will start with no bits set and these will be updated as handlers
@ -483,71 +477,3 @@ stray_irqhandler(mask)
log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
stray_irqs >= 8 ? ": stopped logging" : "");
}
/*
* int fiq_claim(fiqhandler_t *handler)
*
* Claim FIQ's and install a handler for them.
*/
int
fiq_claim(handler)
fiqhandler_t *handler;
{
/* Fail if the FIQ's are already claimed */
if (fiqhandlers)
return(-1);
if (handler->fh_size > 0xc0)
return(-1);
/* Install the handler */
fiqhandlers = handler;
/* Now we have to actually install the FIQ handler */
/* Eventually we will copy this down but for the moment ... */
zero_page_readwrite();
WriteWord(0x0000003c, (u_int) handler->fh_func);
zero_page_readonly();
cpu_cache_syncI_rng(0, 0x40); /* XXX 0x3c should never be in the ic*/
/* We must now set up the FIQ registers */
fiq_setregs(handler);
/* Make sure that the FIQ's are enabled */
enable_interrupts(F32_bit);
return(0);
}
/*
* int fiq_release(fiqhandler_t *handler)
*
* Release FIQ's and remove a handler for them.
*/
int
fiq_release(handler)
fiqhandler_t *handler;
{
/* Fail if the handler is wrong */
if (fiqhandlers != handler)
return(-1);
/* Disable FIQ interrupts */
disable_interrupts(F32_bit);
/* Retrieve the FIQ registers */
fiq_getregs(handler);
/* Remove the handler */
fiqhandlers = NULL;
return(0);
}
/* End of irqhandler.c */

42
sys/arch/arm32/ofw/ofw_irq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: ofw_irq.S,v 1.10 2001/10/29 17:30:26 matt Exp $ */
/* $NetBSD: ofw_irq.S,v 1.11 2001/12/20 01:20:26 thorpej Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -642,43 +642,3 @@ _C_LABEL(intrcnt):
.long 0
_C_LABEL(eintrcnt):
#endif /* IRQSTATS */
/* FIQ code */
ENTRY(fiq_setregs)
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
ldr r9, [r0, #FH_R9]
ldr r10, [r0, #FH_R10]
ldr r11, [r0, #FH_R11]
ldr r12, [r0, #FH_R12]
ldr r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
ENTRY(fiq_getregs)
mrs r2, cpsr_all
mov r3, r2
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_FIQ32_MODE)
msr cpsr_all, r2
str r8, [r0, #FH_R8] /* Update FIQ registers*/
str r9, [r0, #FH_R9]
str r10, [r0, #FH_R10]
str r11, [r0, #FH_R11]
str r12, [r0, #FH_R12]
str r13, [r0, #FH_R13]
msr cpsr_all, r3 /* Back to old mode */
mov pc, lr /* Exit */
/* End of irq.S */

36
sys/arch/arm32/ofw/ofw_irqhandler.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: ofw_irqhandler.c,v 1.10 2001/11/27 01:06:29 thorpej Exp $ */
/* $NetBSD: ofw_irqhandler.c,v 1.11 2001/12/20 01:20:26 thorpej Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@ -72,8 +72,6 @@ extern char *_intrnames;
/* Prototypes */
int podule_irqhandler __P((void));
extern int fiq_setregs __P((fiqhandler_t *));
extern int fiq_getregs __P((fiqhandler_t *));
extern void set_spl_masks __P((void));
/*
@ -485,35 +483,3 @@ stray_irqhandler(mask)
log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
stray_irqs >= 8 ? ": stopped logging" : "");
}
/*
* int fiq_claim(fiqhandler_t *handler)
*
* Claim FIQ's and install a handler for them.
*/
int
fiq_claim(handler)
fiqhandler_t *handler;
{
/* Not supported. */
return(-1);
}
/*
* int fiq_release(fiqhandler_t *handler)
*
* Release FIQ's and remove a handler for them.
*/
int
fiq_release(handler)
fiqhandler_t *handler;
{
/* Not supported. */
return(-1);
}
/* End of ofw_irqhandler.c */

31
sys/arch/arm32/shark/hat.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: hat.c,v 1.7 2001/11/27 01:06:30 thorpej Exp $ */
/* $NetBSD: hat.c,v 1.8 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright 1997
@ -46,6 +46,8 @@
#include <sys/kernel.h>
#include <sys/device.h>
#include <arm/fiq.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/pio.h>
@ -56,12 +58,9 @@
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
#include <arm32/shark/fiq.h>
#include <arm32/shark/shark_fiq.h>
#include <arm32/shark/sequoia.h>
extern int fiq_getregs __P((fiqhandler_t *));
extern int fiq_setregs __P((fiqhandler_t *));
static int hatOn = 0;
/* interface to high-availability timer */
@ -71,9 +70,10 @@ static void hatEnableSWTCH();
static void (*hatWedgeFn)(int);
extern struct fiqregs shark_fiqregs;
int hatClkOff(void)
{
fiqhandler_t fiqhandler;
u_int16_t seqReg;
if (!hatOn) return -1;
@ -89,13 +89,13 @@ int hatClkOff(void)
outb(ATSR_REG1_REG,
inb(ATSR_REG1_REG) & ~((REG1_M_TMR2EN) | (REG1_M_SPKREN)));
fiq_getregs(&fiqhandler);
fiq_getregs(&shark_fiqregs);
/* get rid of the C routine and stack */
fiqhandler.fh_r9 = 0;
fiqhandler.fh_r13 = 0;
shark_fiqregs.fr_r9 = 0;
shark_fiqregs.fr_r13 = 0;
fiq_setregs(&fiqhandler);
fiq_setregs(&shark_fiqregs);
isa_dmathaw(&isa_chipset_tag); /* XXX */
return 0;
@ -105,7 +105,6 @@ int hatClkOff(void)
int hatClkOn(int count, void (*hatFn)(int), int arg,
unsigned char *stack, void (*wedgeFn)(int))
{
fiqhandler_t fiqhandler;
u_int16_t seqReg;
if (hatOn) return -1;
@ -114,14 +113,14 @@ int hatClkOn(int count, void (*hatFn)(int), int arg,
isa_dmafreeze(&isa_chipset_tag); /* XXX */
fiq_getregs(&fiqhandler);
fiq_getregs(&shark_fiqregs);
/* set the C routine and stack */
fiqhandler.fh_r9 = (u_int)hatFn;
fiqhandler.fh_r10 = (u_int)arg;
fiqhandler.fh_r13 = (u_int)stack;
shark_fiqregs.fr_r9 = (u_int)hatFn;
shark_fiqregs.fr_r10 = (u_int)arg;
shark_fiqregs.fr_r13 = (u_int)stack;
fiq_setregs(&fiqhandler);
fiq_setregs(&shark_fiqregs);
/* no debounce on SWTCH */
sequoiaRead(PMC_DBCR_REG, &seqReg);

4
sys/arch/arm32/shark/sequoia.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: sequoia.c,v 1.7 2001/11/23 19:36:49 thorpej Exp $ */
/* $NetBSD: sequoia.c,v 1.8 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright 1997
@ -52,7 +52,7 @@
#include <dev/isa/isareg.h>
#include <machine/isa_machdep.h>
#include <arm32/shark/sequoia.h>
#include <arm32/shark/fiq.h>
#include <arm32/shark/shark_fiq.h>
#include <arm/cpufunc.h>

4
sys/arch/arm32/shark/fiq.S → sys/arch/arm32/shark/shark_fiq.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: fiq.S,v 1.3 1999/10/26 06:53:44 cgd Exp $ */
/* $NetBSD: shark_fiq.S,v 1.1 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright 1997
@ -43,7 +43,7 @@
#include <machine/asm.h>
#include <machine/cpu.h>
#include <arm32/shark/fiq.h>
#include <arm32/shark/shark_fiq.h>
#include <arm32/shark/sequoia.h>
sp .req r13

2
sys/arch/arm32/shark/fiq.h → sys/arch/arm32/shark/shark_fiq.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: fiq.h,v 1.2 1998/05/01 21:18:40 cgd Exp $ */
/* $NetBSD: shark_fiq.h,v 1.1 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright 1997

34
sys/arch/arm32/shark/shark_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: shark_machdep.c,v 1.28 2001/12/02 22:54:26 bouyer Exp $ */
/* $NetBSD: shark_machdep.c,v 1.29 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright 1997
@ -50,6 +50,8 @@
#include <uvm/uvm_extern.h>
#include <arm/fiq.h>
#include <dev/cons.h>
#include <machine/db_machdep.h>
@ -188,6 +190,10 @@ cpu_reboot(howto, bootstr)
* Return the new stackptr (va) for the SVC frame.
*
*/
struct fiqhandler shark_fiqhandler;
struct fiqregs shark_fiqregs;
vm_offset_t
initarm(ofw_handle)
ofw_handle_t ofw_handle;
@ -196,9 +202,7 @@ initarm(ofw_handle)
vm_offset_t isa_io_physaddr, isa_mem_physaddr;
vm_offset_t isa_io_virtaddr, isa_mem_virtaddr;
vm_offset_t isadmaphysbufs;
fiqhandler_t fiqhandler;
extern void shark_fiq __P((void));
extern void shark_fiq_end __P((void));
extern char shark_fiq[], shark_fiq_end[];
/* Don't want to get hit with interrupts 'til we're ready. */
(void)disable_interrupts(I32_bit | F32_bit);
@ -292,17 +296,19 @@ initarm(ofw_handle)
undefined_init();
/* Now for the SHARK-specific part of the FIQ set-up */
fiqhandler.fh_func = shark_fiq;
fiqhandler.fh_size = (char *)shark_fiq_end - (char *)shark_fiq;
fiqhandler.fh_mask = 0x01; /* XXX ??? */
fiqhandler.fh_r8 = isa_io_virtaddr;
fiqhandler.fh_r9 = 0; /* no routine right now */
fiqhandler.fh_r10 = 0; /* no arg right now */
fiqhandler.fh_r11 = 0; /* scratch */
fiqhandler.fh_r12 = 0; /* scratch */
fiqhandler.fh_r13 = 0; /* must set a stack when r9 is set! */
shark_fiqhandler.fh_func = shark_fiq;
shark_fiqhandler.fh_size = shark_fiq_end - shark_fiq;
shark_fiqhandler.fh_flags = 0;
shark_fiqhandler.fh_regs = &shark_fiqregs;
if (fiq_claim(&fiqhandler))
shark_fiqregs.fr_r8 = isa_io_virtaddr;
shark_fiqregs.fr_r9 = 0; /* no routine right now */
shark_fiqregs.fr_r10 = 0; /* no arg right now */
shark_fiqregs.fr_r11 = 0; /* scratch */
shark_fiqregs.fr_r12 = 0; /* scratch */
shark_fiqregs.fr_r13 = 0; /* must set a stack when r9 is set! */
if (fiq_claim(&shark_fiqhandler))
panic("Cannot claim FIQ vector.\n");
#ifdef DDB

21
sys/arch/cats/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.1 2001/06/08 22:23:01 chris Exp $ */
/* $NetBSD: irqhandler.h,v 1.2 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -268,25 +268,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#ifdef _KERNEL
int fiq_claim __P((fiqhandler_t *));
int fiq_release __P((fiqhandler_t *));
#endif /* _KERNEL */
#endif /* _LOCORE */
#endif /* _ARM32_IRQHANDLER_H_ */
/* End of irqhandler.h */

21
sys/arch/evbarm/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.3 2001/11/26 20:26:21 thorpej Exp $ */
/* $NetBSD: irqhandler.h,v 1.4 2001/12/20 01:20:27 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -87,25 +87,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#ifdef _KERNEL
int fiq_claim __P((fiqhandler_t *));
int fiq_release __P((fiqhandler_t *));
#endif /* _KERNEL */
#endif /* _LOCORE */
#endif /* _ARM32_IRQHANDLER_H_ */
/* End of irqhandler.h */

11
sys/arch/evbarm/iq80310/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.1 2001/11/27 00:16:00 thorpej Exp $
# $NetBSD: genassym.cf,v 1.2 2001/12/20 01:20:28 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -44,12 +44,3 @@ define IH_NUM offsetof(struct irqhandler, ih_num)
define IH_MASKADDR offsetof(struct irqhandler, ih_maskaddr)
define IH_MASKBITS offsetof(struct irqhandler, ih_maskbits)
define IH_NEXT offsetof(struct irqhandler, ih_next)
define FH_FUNC offsetof(struct fiqhandler, fh_func)
define FH_R8 offsetof(struct fiqhandler, fh_r8)
define FH_R9 offsetof(struct fiqhandler, fh_r9)
define FH_R10 offsetof(struct fiqhandler, fh_r10)
define FH_R11 offsetof(struct fiqhandler, fh_r11)
define FH_R12 offsetof(struct fiqhandler, fh_r12)
define FH_R13 offsetof(struct fiqhandler, fh_r13)
define FH_MASK offsetof(struct fiqhandler, fh_mask)

3
sys/arch/hpcarm/conf/files.hpcarm
View File

@ -1,4 +1,4 @@
# $NetBSD: files.hpcarm,v 1.32 2001/11/28 10:21:14 lukem Exp $
# $NetBSD: files.hpcarm,v 1.33 2001/12/20 01:20:28 thorpej Exp $
#
# First try for arm-specific configuration info
#
@ -27,7 +27,6 @@ file arch/arm/arm32/conf.c
# Generic MD files
file arch/hpcarm/hpcarm/autoconf.c
file arch/hpcarm/hpcarm/cpuswitch.S
file arch/hpcarm/hpcarm/exception.S
file arch/hpcarm/hpcarm/fault.c
file arch/hpcarm/hpcarm/fusu.S
file arch/hpcarm/hpcarm/intr.c

396
sys/arch/hpcarm/hpcarm/exception.S
View File

@ -1,396 +0,0 @@
/* $NetBSD: exception.S,v 1.1 2001/02/23 03:48:10 ichiro Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* exception.S
*
* Low level handlers for exception vectors
*
* Created : 24/09/94
*
* Based on kate/display/abort.s
*/
#include "opt_ipkdb.h"
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include "assym.h"
.text
.align 0
Lastpending:
.word _C_LABEL(astpending)
/*
* General exception exit handler
*
* It exits straight away if not returning to USR mode.
* This loops around delivering any pending ASTs.
* Interrupts are disabled at suitable points to avoid ASTs
* being posted between testing and exit to user mode.
*
* This function uses PULLFRAMEFROMSVCANDEXIT thus should
* only be called if the exception handler used PUSHFRAMEINSVC
*/
exception_exit:
mrs r4, cpsr /* Get CPSR */
ldr r0, [sp] /* Get the SPSR from stack */
and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the AST */
teq r0, #(PSR_USR32_MODE)
bne do_exit /* Not USR mode so no AST delivery */
ldr r5, Lastpending /* Get address of astpending */
Lexception_exit_loop:
orr r0, r4, #(I32_bit) /* Block IRQs */
msr cpsr, r0
ldr r1, [r5] /* Do we have an AST pending */
teq r1, #0x00000000
bne do_ast
PULLFRAMEFROMSVCANDEXIT /* No AST so exit */
do_ast:
msr cpsr, r4 /* Restore interrupts */
mov r1, #0x00000000 /* Clear ast pending */
str r1, [r5]
mov r0, sp /* arg 0 = trap frame */
bl _C_LABEL(ast) /* call the AST handler */
b Lexception_exit_loop /* Try and exit again */
do_exit:
orr r0, r4, #(I32_bit) /* Disable interupts */
msr cpsr, r0
PULLFRAMEFROMSVCANDEXIT /* Restore the trap frame and exit */
/* entry point for CPU data abort */
ASENTRY_NP(data_abort_entry)
sub lr, lr, #0x00000008 /* Adjust the lr */
PUSHFRAMEINSVC /* Push trap frame and switch */
/* to SVC32 mode */
mov r0, sp /* pass the stack pointer as r0 */
/* add lr, pc, #exception_exitLdata_abort_return - . - 8*/
add lr, pc, #exception_exit - . - 8
ldr r1, Ldata_abort_handler_address
ldr pc, [r1]
Ldata_abort_return: /* XXX - could just straight to exception_exit */
b exception_exit
Ldata_abort_handler_address:
.word _C_LABEL(data_abort_handler_address)
.data
.global _C_LABEL(data_abort_handler_address)
_C_LABEL(data_abort_handler_address):
.word abortdata
.text
abortdata:
add r0, pc, #abortdatamsg - . - 8
b _C_LABEL(panic)
abortdatamsg:
.asciz "abortdata"
.align 0
ASENTRY_NP(prefetch_abort_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC
mov r0, sp /* pass the stack pointer as r0 */
# add lr, pc, #Lprefetch_abort_return - . - 8
add lr, pc, #exception_exit - . - 8
ldr r1, Lprefetch_abort_handler_address
ldr pc, [r1]
Lprefetch_abort_return: /* XXX - could just straight to exception_exit */
b exception_exit
Lprefetch_abort_handler_address:
.word _C_LABEL(prefetch_abort_handler_address)
.data
.global _C_LABEL(prefetch_abort_handler_address)
_C_LABEL(prefetch_abort_handler_address):
.word abortprefetch
.text
abortprefetch:
add r0, pc, #abortprefetchmsg - . - 8
b _C_LABEL(panic)
abortprefetchmsg:
.asciz "abortprefetch"
.align 0
/*
* swi_entry
*
* Main entry point for the SWI vector
*/
ASENTRY_NP(swi_entry)
PUSHFRAME
sub r0, lr, #0x00000004 /* Get the address of the SWI */
ldr r4, [r0] /* Get the instruction */
bic r1, r4, #0xff000000 /* Extract the comment field */
mov r0, sp /* Pass the frame to any function */
bl _C_LABEL(syscall) /* It's a syscall ! */
ldr r5, Lastpending /* Get address of astpending */
mrs r4, cpsr /* Get CPSR */
swi_exit_loop:
orr r0, r4, #(I32_bit) /* Disable IRQs */
msr cpsr, r0
ldr r1, [r5] /* Do we have an AST pending */
teq r1, #0x00000000
bne do_swi_ast
PULLFRAME
movs pc, lr /* Exit */
do_swi_ast:
msr cpsr, r4 /* Restore interrupts */
mov r1, #0x00000000 /* Clear ast pending */
str r1, [r5]
mov r0, sp /* arg 0 = trap frame */
bl _C_LABEL(ast) /* call the AST handler */
b swi_exit_loop /* Try and exit again */
/*
* We indirect the undefined vector via the handler address
* in the data area.
* Entry to the undefined handler must look like direct
* entry from the vector.
*/
ASENTRY_NP(undefined_entry)
#ifdef IPKDB
/*
* IPKDB must be hooked in at the earliest possible entry point.
*
*/
/*
* Make room for all registers saving real r0-r7 and r15.
* The remaining registers are updated later.
*/
stmfd sp!, {r0,r1} /* psr & spsr */
stmfd sp!, {lr} /* pc */
stmfd sp!, {r0-r14} /* r0-r7, r8-r14 */
/*
* Get previous psr.
*/
mrs r7, cpsr
mrs r0, spsr
str r0, [sp, #(16*4)]
/*
* Test for user mode.
*/
tst r0, #0xf
bne Lprenotuser_push
add r1, sp, #(8*4)
stmia r1,{r8-r14}^ /* store user mode r8-r14*/
b Lgoipkdb
/*
* Switch to previous mode to get r8-r13.
*/
Lprenotuser_push:
orr r0, r0, #(I32_bit) /* disable interrupts */
msr cpsr, r0
mov r1, r8
mov r2, r9
mov r3, r10
mov r4, r11
mov r5, r12
mov r6, r13
msr cpsr, r7 /* back to undefined mode */
add r8, sp, #(8*4)
stmia r8, {r1-r6} /* r8-r13 */
/*
* Now back to previous mode to get r14 and spsr.
*/
msr cpsr, r0
mov r1, r14
mrs r2, spsr
msr cpsr, r7 /* back to undefined mode */
str r1, [sp, #(14*4)] /* r14 */
str r2, [sp, #(17*4)] /* spsr */
/*
* Now to IPKDB.
*/
Lgoipkdb:
mov r0, sp
bl _C_LABEL(ipkdb_trap_glue)
ldr r1, Lipkdb_trap_return
str r0,[r1]
/*
* Have to load all registers from the stack.
*
* Start with spsr and pc.
*/
ldr r0, [sp, #(16*4)] /* spsr */
ldr r1, [sp, #(15*4)] /* r15 */
msr spsr, r0
mov r14, r1
/*
* Test for user mode.
*/
tst r0, #0xf
bne Lprenotuser_pull
add r1, sp, #(8*4)
ldmia r1, {r8-r14}^ /* load user mode r8-r14 */
b Lpull_r0r7
Lprenotuser_pull:
/*
* Now previous mode spsr and r14.
*/
ldr r1, [sp, #(17*4)] /* spsr */
ldr r2, [sp, #(14*4)] /* r14 */
orr r0, r0, #(I32_bit)
msr cpsr, r0 /* switch to previous mode */
msr spsr, r1
mov r14, r2
msr cpsr, r7 /* back to undefined mode */
/*
* Now r8-r13.
*/
add r8, sp, #(8*4)
ldmia r8, {r1-r6} /* r8-r13 */
msr cpsr, r0
mov r8, r1
mov r9, r2
mov r10, r3
mov r11, r4
mov r12, r5
mov r13, r6
msr cpsr, r7
Lpull_r0r7:
/*
* Now the rest of the registers.
*/
ldr r1,Lipkdb_trap_return
ldr r0,[r1]
tst r0,r0
ldmfd sp!, {r0-r7} /* r0-r7 */
add sp, sp, #(10*4) /* adjust sp */
/*
* Did IPKDB handle it?
*/
movnes pc, lr /* return */
#endif
stmfd sp!, {r0, r1}
ldr r0, Lundefined_handler_indirection
ldr r1, [sp], #0x0004
str r1, [r0, #0x0000]
ldr r1, [sp], #0x0004
str r1, [r0, #0x0004]
ldmia r0, {r0, r1, pc}
#ifdef IPKDB
Lipkdb_trap_return:
.word Lipkdb_trap_return_data
#endif
Lundefined_handler_indirection:
.word Lundefined_handler_indirection_data
/*
* assembly bounce code for calling the kernel
* undefined instruction handler. This uses
* a standard trap frame and is called in SVC mode.
*/
ENTRY_NP(undefinedinstruction_bounce)
PUSHFRAMEINSVC
mov r0, sp
bl _C_LABEL(undefinedinstruction)
b exception_exit
.data
.align 0
#ifdef IPKDB
Lipkdb_trap_return_data:
.word 0
#endif
/*
* Indirection data
* 2 words use for preserving r0 and r1
* 3rd word contains the undefined handler address.
*/
Lundefined_handler_indirection_data:
.word 0
.word 0
.global _C_LABEL(undefined_handler_address)
_C_LABEL(undefined_handler_address):
.word _C_LABEL(undefinedinstruction_bounce)
/* End of exception.S */

95
sys/arch/hpcarm/hpcarm/genassym.cf
View File

@ -1,4 +1,4 @@
# $NetBSD: genassym.cf,v 1.5 2001/09/09 10:33:43 toshii Exp $
# $NetBSD: genassym.cf,v 1.6 2001/12/20 01:20:28 thorpej Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@ -34,73 +34,8 @@
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
include <sys/param.h>
include <sys/systm.h>
include <sys/proc.h>
include <sys/resourcevar.h>
include <sys/device.h>
include <sys/user.h>
include <sys/signal.h>
include <uvm/uvm_extern.h>
include <machine/pmap.h>
include <machine/frame.h>
include <machine/vmparam.h>
include <machine/irqhandler.h>
define VM_MIN_ADDRESS VM_MIN_ADDRESS
define VM_MAXUSER_ADDRESS VM_MAXUSER_ADDRESS
define VM_MAXKERN_ADDRESS VM_MAXKERN_ADDRESS
define PROCESS_PAGE_TBLS_BASE PROCESS_PAGE_TBLS_BASE
define UPAGES UPAGES
define PGSHIFT PGSHIFT
define PDSHIFT PDSHIFT
define P_TRACED P_TRACED
define P_PROFIL P_PROFIL
define P_ADDR offsetof(struct proc, p_addr)
define P_BACK offsetof(struct proc, p_back)
define P_FORW offsetof(struct proc, p_forw)
define P_PRIORITY offsetof(struct proc, p_priority)
define P_STAT offsetof(struct proc, p_stat)
define P_WCHAN offsetof(struct proc, p_wchan)
define P_VMSPACE offsetof(struct proc, p_vmspace)
define P_FLAG offsetof(struct proc, p_flag)
define P_SIGLIST offsetof(struct proc, p_sigctx) + offsetof(struct sigctx, ps_siglist)
define P_SIGMASK offsetof(struct proc, p_sigctx) + offsetof(struct sigctx, ps_sigmask)
define P_USRPRI offsetof(struct proc, p_usrpri)
define SONPROC SONPROC
define PCB_PAGEDIR offsetof(struct pcb, pcb_pagedir)
define PCB_FLAGS offsetof(struct pcb, pcb_flags)
define PCB_R8 offsetof(struct pcb, pcb_un.un_32.pcb32_r8)
define PCB_R9 offsetof(struct pcb, pcb_un.un_32.pcb32_r9)
define PCB_R10 offsetof(struct pcb, pcb_un.un_32.pcb32_r10)
define PCB_R11 offsetof(struct pcb, pcb_un.un_32.pcb32_r11)
define PCB_R12 offsetof(struct pcb, pcb_un.un_32.pcb32_r12)
define PCB_SP offsetof(struct pcb, pcb_un.un_32.pcb32_sp)
define PCB_LR offsetof(struct pcb, pcb_un.un_32.pcb32_lr)
define PCB_PC offsetof(struct pcb, pcb_un.un_32.pcb32_pc)
define PCB_UND_SP offsetof(struct pcb, pcb_un.un_32.pcb32_und_sp)
define PCB_ONFAULT offsetof(struct pcb, pcb_onfault)
define USER_SIZE sizeof(struct user)
define V_TRAP offsetof(struct uvmexp, traps)
define V_INTR offsetof(struct uvmexp, intrs)
define V_SOFT offsetof(struct uvmexp, softs)
define VM_MAP offsetof(struct vmspace, vm_map)
define VM_PMAP offsetof(struct vmspace, vm_map.pmap)
define PR_BASE offsetof(struct uprof, pr_base)
define PR_SIZE offsetof(struct uprof, pr_size)
define PR_OFF offsetof(struct uprof, pr_off)
define PR_SCALE offsetof(struct uprof, pr_scale)
define IH_FUNC offsetof(irqhandler_t, ih_func)
define IH_ARG offsetof(irqhandler_t, ih_arg)
define IH_LEVEL offsetof(irqhandler_t, ih_level)
@ -109,31 +44,3 @@ define IH_FLAGS offsetof(irqhandler_t, ih_flags)
define IH_MASKADDR offsetof(irqhandler_t, ih_maskaddr)
define IH_MASKBITS offsetof(irqhandler_t, ih_maskbits)
define IH_NEXT offsetof(irqhandler_t, ih_next)
define FH_FUNC offsetof(fiqhandler_t, fh_func)
define FH_MASK offsetof(fiqhandler_t, fh_mask)
define FH_R8 offsetof(fiqhandler_t, fh_r8)
define FH_R9 offsetof(fiqhandler_t, fh_r9)
define FH_R10 offsetof(fiqhandler_t, fh_r10)
define FH_R11 offsetof(fiqhandler_t, fh_r11)
define FH_R12 offsetof(fiqhandler_t, fh_r12)
define FH_R13 offsetof(fiqhandler_t, fh_r13)
define SIGF_HANDLER offsetof(struct sigframe, sf_handler)
define SIGF_SC offsetof(struct sigframe, sf_sc)
define SIGTRAP SIGTRAP
define SIGEMT SIGEMT
define TF_R0 offsetof(struct trapframe, tf_r0)
define TF_R10 offsetof(struct trapframe, tf_r10)
define TF_PC offsetof(struct trapframe, tf_pc)
define PROCSIZE sizeof(struct proc)
define TRAPFRAMESIZE sizeof(struct trapframe)
define CF_CACHE_PURGE_ID offsetof(struct cpu_functions, cf_cache_purgeID)
define CF_CONTEXT_SWITCH offsetof(struct cpu_functions, cf_context_switch)
define CF_SLEEP offsetof(struct cpu_functions, cf_sleep)
define CI_CURPRIORITY offsetof(struct cpu_info, ci_schedstate.spc_curpriority)

102
sys/arch/hpcarm/hpcarm/locore.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: locore.S,v 1.3 2001/06/01 14:04:29 toshii Exp $ */
/* $NetBSD: locore.S,v 1.4 2001/12/20 01:20:28 thorpej Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
@ -90,74 +90,8 @@ ASENTRY_NP(start)
b .
/*
* Instructions to copy to the bottom of zero page
* These are the entry point to the system exception routines
*/
.text
.align 0
.global _C_LABEL(page0), _C_LABEL(page0_end)
_C_LABEL(page0):
ldr pc, [pc, #Lreset - . - 8]
ldr pc, [pc, #Lundefined - . - 8]
ldr pc, [pc, #Lswi - . - 8]
ldr pc, [pc, #Labortpre - . - 8]
ldr pc, [pc, #Labortdata - . - 8]
ldr pc, [pc, #Laddrexc - . - 8]
ldr pc, [pc, #Lirq - . - 8]
ldr pc, [pc, #Lfiq - . - 8]
Lreset:
.word reset_entry
Lundefined:
.word undefined_entry
Lswi:
.word swi_entry
Labortpre:
.word prefetch_abort_entry
Labortdata:
.word data_abort_entry
Laddrexc:
.word addrexc
Lirq:
.word irq_entry
Lfiq:
.word fiq
_C_LABEL(page0_end) = .
/* vector 0x00000000 - RESET */
ASENTRY_NP(reset_entry)
PUSHFRAME
mov r0, sp /* Pass the frame to function */
b _C_LABEL(resethandler) /* It's a branch throught zero ! */
/* vector 0x00000008 - ADDRESS EXCEPTION */
ASENTRY_NP(addrexc)
mrs r1, cpsr
mrs r2, spsr
mov r3, lr
add r0, pc, #Laddrexcmsg - . - 8
bl _C_LABEL(printf)
b data_abort_entry
Laddrexcmsg:
.asciz "address exception CPSR=%08x SPSR=%08x lr=%08x\n"
.align 0
/* vector 0x0000001C - FIQ */
ASENTRY_NP(fiq)
ldr r0, Lfiqmsg
b _C_LABEL(panic)
Lfiqmsg:
.asciz "fiq"
.align 0
Lcpufuncs:
.word _C_LABEL(cpufuncs)
@ -197,40 +131,6 @@ Lcpu_reset_address:
.word _C_LABEL(cpu_reset_address)
#ifdef IPKDB
#if 0
/*
* ipkdbfbyte and ipkdbsbyte are now in ipkdb_glue.c and do not tweak
* the abort handler anymore
*/
ENTRY_NP(ipkdbfbyte)
ldr ip, abortp
ldr r2, [ip]
add r3, pc, #ipkdbfault - . - 8
str r3, [ip]
ldrb r0, [r0]
str r2, [ip]
mov pc, lr
ENTRY_NP(ipkdbsbyte)
ldr ip, abortp
ldr r2, [ip]
add r3, pc, #ipkdbfault - . - 8
str r3, [ip]
strb r1, [r0]
sub r0, r0, r0
str r2, [ip]
mov pc, lr
abortp:
.word Labortdata - _C_LABEL(page0)
ipkdbfault:
mov r0, #0xd3
msr cpsr, r0
mvn r0, #0 /* mov r0, #-1 */
str r2, [ip]
mov pc, lr
#endif
/*
* Execute(inst, psr, args, sp)
*

17
sys/arch/hpcarm/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.3 2001/05/30 12:28:43 mrg Exp $ */
/* $NetBSD: irqhandler.h,v 1.4 2001/12/20 01:20:29 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -89,21 +89,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#endif /* _LOCORE */
#endif /* _HPCARM_IRQHANDLER_H_ */
/* End of irqhandler.h */

21
sys/arch/netwinder/include/irqhandler.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: irqhandler.h,v 1.2 2001/05/30 12:28:47 mrg Exp $ */
/* $NetBSD: irqhandler.h,v 1.3 2001/12/20 01:20:29 thorpej Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -268,25 +268,6 @@ void enable_irq __P((int));
#define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */
#ifndef _LOCORE
typedef struct fiqhandler {
void (*fh_func) __P((void));/* handler function */
u_int fh_size; /* Size of handler function */
u_int fh_mask; /* FIQ mask */
u_int fh_r8; /* FIQ mode r8 */
u_int fh_r9; /* FIQ mode r9 */
u_int fh_r10; /* FIQ mode r10 */
u_int fh_r11; /* FIQ mode r11 */
u_int fh_r12; /* FIQ mode r12 */
u_int fh_r13; /* FIQ mode r13 */
} fiqhandler_t;
#ifdef _KERNEL
int fiq_claim __P((fiqhandler_t *));
int fiq_release __P((fiqhandler_t *));
#endif /* _KERNEL */
#endif /* _LOCORE */
#endif /* _ARM32_IRQHANDLER_H_ */
/* End of irqhandler.h */