Sprinkle CPWAIT around to enforce some barriers. Also deal with some
pre-B-step errata: must clean-dcache-line to an address before invalidate-dcache-line to that address, or the dirty bits will not get cleanred in the dcache array for that line.
This commit is contained in:
thorpej
parent
3de224080a
commit
8ec81cf263
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@ -1,7 +1,42 @@
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/* $NetBSD: cpufunc_asm_xscale.S,v 1.5 2001/11/19 18:40:15 thorpej Exp $ */
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/* $NetBSD: cpufunc_asm_xscale.S,v 1.6 2001/11/26 18:09:08 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Matt Thomas
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2001 Matt Thomas.
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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@ -46,15 +81,18 @@ Lblock_userspace_access:
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* CPWAIT -- Canonical method to wait for CP15 update.
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* From: Intel 80200 manual, section 2.3.3.
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*
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* NOTE: Clobbers r0.
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* NOTE: Clobbers the specified temp reg.
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*/
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#define CPWAIT \
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mrc p15, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov r0, r0 /* wait for it to complete */ ;\
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sub pc, pc, #4 /* branch to next insn */
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov tmp, tmp /* wait for it to complete */ ;\
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CPWAIT_BRANCH /* branch to next insn */
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ENTRY(xscale_cpwait)
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CPWAIT
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CPWAIT(r0)
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mov pc, lr
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/*
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@ -71,6 +109,9 @@ ENTRY(xscale_control)
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mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
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mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
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mov r0, r3 /* Return old value */
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CPWAIT(r1)
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mov pc, lr
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/*
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@ -92,10 +133,13 @@ ENTRY(xscale_setttb)
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#endif
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stmfd sp!, {r0-r3, lr}
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bl _C_LABEL(xscale_cache_cleanID)
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ldmfd sp!, {r0-r3, lr}
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
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mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
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CPWAIT(r0)
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ldmfd sp!, {r0-r3, lr}
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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@ -105,7 +149,7 @@ ENTRY(xscale_setttb)
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/* The cleanID above means we only need to flush the I cache here */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
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CPWAIT
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CPWAIT(r0)
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#ifdef CACHE_CLEAN_BLOCK_INTR
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msr cpsr_all, r3
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@ -116,6 +160,9 @@ ENTRY(xscale_setttb)
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/*
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* TLB functions
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*
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* Note: We don't need to worry about issuing a CPWAIT after
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* TLB operations, because we expect a pmap_update() to follow.
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*/
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ENTRY(xscale_tlb_flushID_SE)
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mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
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@ -127,26 +174,38 @@ ENTRY(xscale_tlb_flushID_SE)
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*/
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ENTRY(xscale_cache_flushID)
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mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_flushI)
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_flushD)
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mcr p15, 0, r0, c7, c6, 0 /* flush D cache */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_flushI_SE)
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mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_flushD_SE)
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/*
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* Errata (rev < 2): Must clean-dcache-line to an address
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* before invalidate-dcache-line to an address, or dirty
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* bits will not be cleared in the dcache array.
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*/
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mcr p15, 0, r0, c7, c10, 1
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_cleanD_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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CPWAIT(r0)
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mov pc, lr
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/*
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@ -249,22 +308,30 @@ ENTRY(xscale_cache_cleanD)
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bne 1b
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#endif
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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XSCALE_CACHE_CLEAN_EPILOGUE
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mov pc, lr
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ENTRY(xscale_cache_purgeID_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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CPWAIT(r1)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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CPWAIT(r1)
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mov pc, lr
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ENTRY(xscale_cache_purgeD_E)
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mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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CPWAIT(r1)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
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CPWAIT(r1)
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mov pc, lr
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/*
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@ -286,7 +353,12 @@ ENTRY(xscale_cache_cleanD_rng)
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subs r1, r1, #32
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bpl 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_purgeID_rng)
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@ -304,7 +376,12 @@ ENTRY(xscale_cache_purgeID_rng)
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subs r1, r1, #32
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bpl 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_purgeD_rng)
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@ -321,7 +398,12 @@ ENTRY(xscale_cache_purgeD_rng)
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subs r1, r1, #32
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bpl 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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ENTRY(xscale_cache_syncI_rng)
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@ -338,7 +420,12 @@ ENTRY(xscale_cache_syncI_rng)
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subs r1, r1, #32
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bpl 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT(r0)
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mov pc, lr
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/*
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@ -364,6 +451,6 @@ ENTRY(xscale_context_switch)
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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CPWAIT
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CPWAIT(r0)
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mov pc, lr
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