- Add alignment-safe double and float unions.
- Use the above for the __infinity and __nan constants on all
architectures that use the standard ieee754 representation of
those constants.
- Add a single copy of various ieee754 math functions (frexp, isinf,
isnan, ldexp and modf) that had numerous duplicates among the
arch-specific directories.
- Use the above functions on all architectures where the generic C
versions where used. Architectures that had local assembly
routines are untouched (for those functions only).
MACHINE_ARCH since <arm/param.h> already sets it correctly to "arm".
* For platforms which are not yet ELF, defined MACHINE_ARCH to "arm32"
if __ELF__ is not defined by the C preprocessor.
* In <arm/param.h>, clarify the rules about when MACHINE and
MACHINE_ARCH are defined, and to what. Also, for ELF platforms,
int the non-_KERNEL case, force both MACHINE and MACHINE_ARCH to "arm",
rather than allowing platform-specifc code to define either.
enabled by definining __ARM_FIQ_INDIRECT in <machine/types.h>.
This is needed for OpenFirmware systems (like the Shark), where
the OFW vector page is used, and kernel entries merely patched
into it.
interrupt code for the IQ80310 board support package.
XXX The Integrator board support package still uses the old-style
arm32 interrupt code, so some compatibility hacks have been added
for it. When the Integrator uses new-style interrupts, those hacks
can go away.
Those for the SA-1100 and SA-1110 are from Intel's documentation.
The mapping for the SA-110 is from various sources on the net, since Intel
don't seem to document it.
Also, change the layout of the maps to have four steppings per line,
so they aren't quite so unwieldy.
cores.
* For i80200 Step-A0 and Step-A1, set dcache_inv_range to
xscale_cache_purgeD_rng to work around a bug where a D$
"invalidate by address" doesn't properly clear the dirty
bits on the cache block (i80200 errata item #25).
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$
More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:
icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range
dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range
idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range
Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.
use 2 adjacent cache-size areas for global cache clean, alternating
between the two of them on each call. Without this, D-cache blocks
aren't evicted properly, and no one seems to know why.
1) Add defparam XSCALE_CCLKCFG to define a parameter for the
CCLKCFG register. Default it to '9' on the IQ80310.
2) Add a sleep call to the xscale CPU function vector (replacing
the nullop) which should drop the CPU into "idle" mode when
cpu_switch finds nothing on the run queues.
by SWI numbers above 0x9f0000, but we re-map them down to somewhere just
after the end of the usual syscall range, since NetBSD doesn't handle
sparse syscall arrays well.
The only syscall I've actually implemented in this range is cacheflush(),
which was previously being mapped to fork(), causing ... interesting results.
swi_handler() does stuff that all SWIs will need, then calls
curproc->p_emul->e_syscall.
syscall() handles native NetBSD system calls.
linux_syscall() handles Linux system calls.
Also update the funcs in arm32_machdep.c that create the entries so that on cats they expect the 2 pagetables to be contiguous, note this means that for now cats is special cased in lots of funcs. I'll tidy this up to something a bit more sane soon, to avoid the multitude of #ifndef cats that I had to sprinkle in.
Note that this leaves a few inconsistencies (no more than we already had though) eg initarm is now prototyped in arm32/machdep.h, however only cats currently makes use of that header.
on a page boundary and can be mapped straight into zero page. This means it
has to be in MD_SFILES on arm26, and not in SFILES.
This probably leaves kernel_text in the wrong place, but it at least leaves the system bootable.
Original i386 log message:
Optimize the case of writing to /dev/zero, and clean up the
surrounding code a bit. Partly suggested by gwr.
I think this needs to be applied to arm26 as well.
* Use a common set of exception handlers for all arm32 platforms.
* New FIQ framework based on discussions with Ben Harris, shared
between arm26 and arm32.
parameters from first principles rather than using a static table for some
rates. This makes it work correctly on ARM7500, for which the table was
bogus (ARM7500 has a different refclk from VIDC20).
Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true. Also appears we're actually missing some, eg the ld block device.
Any problems reported by testers have been fixed, and massive
cross-compiling of kernels has shown that any problems that remain
with actually building kernels are not related to this.
The tmpx registers are now outputs, this makes them all unique.
Add the fact that cc is changed by the asm (not believed to be used but rather be correct)
Correctly specify w as an input and output register, I think this was hiding the bug below!
Allow sum to be in a different input and output register.
Correct bug in psuedo header handling for in4_cksum. Seems that the new macros turned up a latent bug in the psuedo header handling, the code was moving a pointer forward 16 bytes twice, not found before as the ADD16 macro wasn't 100% accurate, as it didn't output w, even though it modified it.
only the Secondary PCI bus (it's the only bus which can have a
device space hidden from any PCI host on the Primary bus).
Also, use the bus number from the PPB businfo register seecondary bus
field rather than hard-coding "1".
not support a value (e.g., it's to be used as "options FOO" instead of
"options FOO=xxx"). options that take a value were converted to
defparam recently.
- minor whitespace & formatting cleanups
pre-B-step errata: must clean-dcache-line to an address before
invalidate-dcache-line to that address, or the dirty bits will not
get cleanred in the dcache array for that line.
broke too many assumptions makde by other parts of the source tree,
and the strategy and how it was supposed to work was never discussed
on tech-userlevel, nor was it applied consistently (to all ARM ports
and to other ports which have common MACHINE_ARCH code, such as MIPS,
m68k, powerpc).
Verified to complete a full "make build" on cats, dnard, evbarm,
and netwinder.
<arm/arm32/vmparam.h> (mostly the stuff that's tied to the pmap
implementation).
- Since the MMU definitions in pte.h are specific to ARM processors
that support 32-bit mode, move pte.h to <arm/arm32/pte.h>.
- Make the Netwinder startup file build again (use PT_B|PT_C, rather
than PT_CACHEABLE, since the latter expands to a variable these days).
model in use for a given platform (__PROG26 vs __PROG32), then pulls
in <arm/types.h>. Change each ARM port to pull in <arm/arm26/types.h>
or <arm/arm32/types.h> as appropriate. Change all references to PROG26
and PROG32 to __PROG26 and __PROG32. Eliminate the opt_progmode.h
header file.
- replace opt_kgdb_machdep.h with opt_kgdb.h
- defparam opt_kgdb.h:
KGDB_DEV KGDB_DEVNAME KGDB_DEVADDR KGDB_DEVRATE KGDB_DEVMODE
- move from opt_ddbparam.h to opt_ddb.h:
DDB_FROMCONSOLE DDB_ONPANIC DDB_HISTORY_SIZE DDB_BREAK_CHAR SYMTAB_SPACE
- replace KGDBDEV with KGDB_DEV
- replace KGDBADDR with KGDB_DEVADDR
- replace KGDBMODE with KGDB_DEVMODE
- replace KGDBRATE with KGDB_DEVRATE
- use `9600' instead of `0x2580' for 9600 baud rate
- use correct quotes for options KGDB_DEVNAME="\"com\""
- use correct quotes for options KGDB_DEV="17*256+0"
- remove unnecessary dependancy on Makefile for kgdb_stub.o
- minor whitespace cleanup
switch_exit only needs to take 1 parameter, it loads the value of proc0 into R1 itself
Fixup some comments to reflect the real state of things.
Tweak a couple of bits of asm to avoid a load delay.
remove excess code for setting curpcb and curproc.
this insn is available only on ARM arch v3 and later (and 2a). We
don't expect to be using these ops in the kernel on processors too
old to have SWP, and for userland uses (in e.g. a pthread library),
the kernel will simply have to trap and emulate the insn (it needs
to be "atomic", so a kernel trap of some sort will be necessary on
such platforms anyway).
the Branch Target Buffer of the BPRD bit changes.
* Enable Branch Prediction on the XScale by default.
* Don't invalidate the Branch Target Buffer explicitly. the i80200
manual (section 5.1, Branch Target Buffer Operation) notes that
manual software management of the BTB is unnecessary; it is flushed
implicitly when:
* processor resets
* FCSE process ID is written
* I-cache is invalidated
* sa110_cache_purgeD() is the same as sa110_cache_cleanD() on the
SA-1 -- make it an alias.
* sa110_cache_syncI() and sa110_cache_purgeID() are identical to
sa110_cache_cleanD() on the SA-1, with the exception that the
I-cache must also be flushed. Save code duplication by moving
the I-cache flush before the D-cache clean and letting it fall
through.
* Define a CPWAIT macro as described in the i80200 manual and use it,
rather than replicating the code in a few places.
* The i80200 manual notes that the line-allocate operation used to
do global D$ clean does not actually perform a load/fill request
from external memory, and thus does not actually place valid data
in the cache lines allocated. Require that machine-dependent code
allocate an appropriately-sized chunk of unmapped VA space for the
global clean operation in order to avoid unpredictable results.
* The i80200 manual notes that the VA range for the Mini-Data global
clean (which *must* be mapped to physical memory) must be reserved
exclusively for cleaning the Mini-Data cache. Require that machine-
dependent code allocate an appropriately-sized chunk of memory for
this purpose.
pages, we use the standard (4K) page size as PAGE_SIZE. Make the
PAGE_SIZE related variables compile-time constants that reflect this.
Results in a bit over 2K worth of .text savings, and visibly better
code in the places that use PAGE_SIZE, etc.
DMA via the Secondary Inbound window, for now. Will probably
need to revisit this at some point.
Require that the board-specific i80312 front-end slice off a
subregion for the memory controller before calling i80312_attach(),
and fix a bug in the IQ80310 front-end that caused the Secondary
Inbound window to be configured incorrectly.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE. On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.
just basic Inbound and Outbound window setup is done, PCI configuration
space access (not quite working yet), and I/O and Memory space routines
so far.
we need later in the code. This fixes a fatal kernel fault in
pmap_modified_emulation if a user application tries to access a kernel
address that is section-mapped.
Add a diagnostic that detects attempts to call pmap_kenter_pa with a
va that is section-mapped.
caching on for a page just because we are clearing the writable bit in
the PTE: this is incompatible with the way pmap_vac_me_harder works,
and the code in the modified emulation handler doesn't know about
recalculating the cachable attributes (nor should it, IMO).
Also, if we are invalidating a page, flush its TLB entry; for some
reason we were only doing this when clearing the Write or modified
bits.
These patches together seem to solve the random seg-faults that were
still occuring occasionally under heavy paging.
is higher than SPL_HIGH (maybe we should be fixing SPL_HIGH).
If IPL_STATCLOCK is defined, initialize spl_masks[_SPL_STATCLOCK] from
it; otherwise initialize use IPL_CLOCK.
the etc Makefile override that by putting USETOOLS into $.MAKEOVERRIDES
This way the default for kernel compiles is still to use the installed
toolchain instead of depending on $TOOLDIR. $TOOLDIR can be used by
simply adding USETOOLS=yes to the command line as usual.
Adjust each ports template to set the default no setting and also pull in
bsd.own.mk if they weren't already to ensure they'll build correctly
with the new toolchain setup.
support it in the kernel yet. If we don't do this, GDB arbitrarily
assumes we wanted it to be 9, which is silly.
In the kernel, leave it undefined so that sys_process.c doesn't
generate code for it.
the instruction we used with GDB 4.x. The new instruction has the advantage
of fitting the pattern that ARM recommend using for instructions that need to
stay undefined.
(eg ARM920), the mode in which the processor operates is governed by
the use of both the PT_C and PT_B bits:
PT_C=1,PT_B=1 -> Write-back
PT_C=1,PT_B=0 -> Write-through
To support this define pte_cache_mode (initialized to PT_C|PT_B) and
use that when enabling cacheing for a page.
to allocate a L1 pt is often enough to bring the system to its knees:
so make the messages PDEBUG(0,...).
However, even with this step having more than a small number of
processes searching for a L1 pt can still be enough to bring the system
down, since they all run at high priority and sleep for very little time,
thus blocking out user code from completing. So implement an exponential
backoff when waiting for a page table, so that we don't hog the CPU when
memory is scarce.
Tested by running a make of the C compiler with "gnumake -j30" (and plenty
of swap space).
is shared with another process (as can happen if vfork is being used),
then that other process will end up not having a page 0, which is bad
news indeed, since then there is no way back into the kernel.
Found this using a multi-ice box, so they are useful after all!
This seems to fix pr port-arm32/11921 and (possibly) kern/9859.
arch/arm/iomd/* .... the RC7500 isnt really an iomd/vidc machine but has
different video/audio chip and was kind of hardwired/hacked into the other
chip drivers.
The IOMD/VIDC combination is now moved to arch/arm/iomd together. These
files still need a lot of cleaning up :( .... esp. the RC7500 support that
is still dormant in it; this needs either to be removed or split out for
RC7500's ``VIDC'' video/audio variant.
Apart from the RC7500 support wich is still in arch/arm32 the
iomd,vidc,riscpc and podulebus subdirectories of arch/arm32 can be removed.
This split still uses some small parts of arch/arm32 .... those are the MI
parts that haven't been moved yet.
RiscPC/A7000 have been tested and confirmed to build as should NC.
- remove special treatment of pager_map mappings in pmaps. this is
required now, since I've removed the globals that expose the address range.
pager_map now uses pmap_kenter_pa() instead of pmap_enter(), so there's
no longer any need to special-case it.
- eliminate struct uvm_vnode by moving its fields into struct vnode.
- rewrite the pageout path. the pager is now responsible for handling the
high-level requests instead of only getting control after a bunch of work
has already been done on its behalf. this will allow us to UBCify LFS,
which needs tighter control over its pages than other filesystems do.
writing a page to disk no longer requires making it read-only, which
allows us to write wired pages without causing all kinds of havoc.
- use a new PG_PAGEOUT flag to indicate that a page should be freed
on behalf of the pagedaemon when it's unlocked. this flag is very similar
to PG_RELEASED, but unlike PG_RELEASED, PG_PAGEOUT can be cleared if the
pageout fails due to eg. an indirect-block buffer being locked.
this allows us to remove the "version" field from struct vm_page,
and together with shrinking "loan_count" from 32 bits to 16,
struct vm_page is now 4 bytes smaller.
- no longer use PG_RELEASED for swap-backed pages. if the page is busy
because it's being paged out, we can't release the swap slot to be
reallocated until that write is complete, but unlike with vnodes we
don't keep a count of in-progress writes so there's no good way to
know when the write is done. instead, when we need to free a busy
swap-backed page, just sleep until we can get it busy ourselves.
- implement a fast-path for extending writes which allows us to avoid
zeroing new pages. this substantially reduces cpu usage.
- encapsulate the data used by the genfs code in a struct genfs_node,
which must be the first element of the filesystem-specific vnode data
for filesystems which use genfs_{get,put}pages().
- eliminate many of the UVM pagerops, since they aren't needed anymore
now that the pager "put" operation is a higher-level operation.
- enhance the genfs code to allow NFS to use the genfs_{get,put}pages
instead of a modified copy.
- clean up struct vnode by removing all the fields that used to be used by
the vfs_cluster.c code (which we don't use anymore with UBC).
- remove kmem_object and mb_object since they were useless.
instead of allocating pages to these objects, we now just allocate
pages with no object. such pages are mapped in the kernel until they
are freed, so we can use the mapping to find the page to free it.
this allows us to remove splvm() protection in several places.
The sum of all these changes improves write throughput on my
decstation 5000/200 to within 1% of the rate of NetBSD 1.5
and reduces the elapsed time for "make release" of a NetBSD 1.5
source tree on my 128MB pc to 10% less than a 1.5 kernel took.
skrll