Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
This commit is contained in:
thorpej
parent
8ed8f67cf7
commit
4e990d9ccb
@ -1,4 +1,4 @@
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/* $NetBSD: rpc_machdep.c,v 1.9 2002/01/07 21:40:59 bjh21 Exp $ */
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/* $NetBSD: rpc_machdep.c,v 1.10 2002/01/25 19:19:22 thorpej Exp $ */
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/*
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* Copyright (c) 2000-2001 Reinoud Zandijk.
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@ -796,7 +796,7 @@ initarm_new_bootloader(bootconf)
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* After booting there are no gross reloations of the kernel thus
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* this problem will not occur after initarm().
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*/
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cpu_cache_cleanID();
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cpu_idcache_wbinv_all();
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/* if there is support for a serial console ...we should now reattach it */
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/* fcomcndetach();*/
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@ -827,7 +827,7 @@ initarm_new_bootloader(bootconf)
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memcpy((char *)0x00000000, page0, page0_end - page0);
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/* We have modified a text page so sync the icache */
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cpu_cache_syncI_rng(0, page0_end - page0);
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cpu_icache_sync_range(0, page0_end - page0);
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#ifdef VERBOSE_INIT_ARM
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printf("\n");
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@ -1375,7 +1375,7 @@ initarm_old_bootloader(bootconf)
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* After booting there are no gross reloations of the kernel thus
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* this problem wil not occur after initarm().
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*/
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cpu_cache_cleanID();
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cpu_idcache_wbinv_all();
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/*
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* Since we have mapped the VRAM up into kernel space we must
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@ -1732,7 +1732,7 @@ initarm_old_bootloader(bootconf)
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* After booting there are no gross reloations of the kernel thus
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* this problem will not occur after initarm().
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*/
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cpu_cache_cleanID();
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cpu_idcache_wbinv_all();
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if (videodram_size != 0) {
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bootconfig.display_start = VMEM_VBASE;
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@ -1750,7 +1750,7 @@ initarm_old_bootloader(bootconf)
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memcpy((char *)0x00000000, page0, page0_end - page0);
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/* We have modified a text page so sync the icache */
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cpu_cache_syncI_rng(0, page0_end - page0);
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cpu_icache_sync_range(0, page0_end - page0);
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/*
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* Pages were allocated during the secondary bootstrap for the
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@ -1,4 +1,4 @@
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/* $NetBSD: esc.c,v 1.3 2001/11/27 00:53:12 thorpej Exp $ */
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/* $NetBSD: esc.c,v 1.4 2002/01/25 19:19:23 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Scott Stevens
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@ -208,7 +208,7 @@ escinitialize(dev)
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pte = pmap_pte(pmap_kernel(), (vm_offset_t)dev->sc_bump_va);
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*pte &= ~PT_C;
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cpu_tlb_flushD();
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cpu_cache_purgeD_rng((vm_offset_t)dev->sc_bump_va, NBPG);
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cpu_dcache_wbinv_range((vm_offset_t)dev->sc_bump_va, NBPG);
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printf(" dmabuf V0x%08x P0x%08x", (u_int)dev->sc_bump_va, (u_int)dev->sc_bump_pa);
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}
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@ -873,7 +873,7 @@ esc_setup_nexus(dev, nexus, pendp, cbuf, clen, buf, len, mode)
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/* Flush the caches. */
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if (len && !(mode & ESC_SELECT_I))
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cpu_cache_purgeD_rng((vm_offset_t)buf, len);
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cpu_dcache_wbinv_range((vm_offset_t)buf, len);
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}
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int
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@ -1,4 +1,4 @@
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/* $NetBSD: sfas.c,v 1.3 2001/11/27 00:53:12 thorpej Exp $ */
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/* $NetBSD: sfas.c,v 1.4 2002/01/25 19:19:23 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Scott Stevens
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@ -209,7 +209,7 @@ sfasinitialize(dev)
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pte = pmap_pte(pmap_kernel(), (vm_offset_t)dev->sc_bump_va);
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*pte &= ~(PT_C | PT_B);
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cpu_tlb_flushD();
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cpu_cache_purgeD_rng((vm_offset_t)dev->sc_bump_va, NBPG);
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cpu_dcache_wbinv_range((vm_offset_t)dev->sc_bump_va, NBPG);
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printf(" dmabuf V0x%08x P0x%08x", (u_int)dev->sc_bump_va, (u_int)dev->sc_bump_pa);
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}
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@ -798,7 +798,7 @@ sfas_setup_nexus(dev, nexus, pendp, cbuf, clen, buf, len, mode)
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/* Flush the caches. */
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if (len && !(mode & SFAS_SELECT_I))
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cpu_cache_purgeD_rng((vm_offset_t)buf, len);
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cpu_dcache_wbinv_range((vm_offset_t)buf, len);
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}
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int
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.26 2002/01/24 04:23:19 briggs Exp $ */
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/* $NetBSD: cpufunc.c,v 1.27 2002/01/25 19:19:24 thorpej Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -103,24 +103,18 @@ struct cpu_functions arm3_cpufuncs = {
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cpufunc_nullop, /* tlb_flushD */
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(void *)cpufunc_nullop, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm3_cache_flush, /* cache_flushID */
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(void *)arm3_cache_flush, /* cache_flushID_SE */
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arm3_cache_flush, /* cache_flushI */
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(void *)arm3_cache_flush, /* cache_flushI_SE */
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arm3_cache_flush, /* cache_flushD */
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(void *)arm3_cache_flush, /* cache_flushD_SE */
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cpufunc_nullop, /* icache_sync_all */
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(void *) cpufunc_nullop, /* icache_sync_range */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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arm3_cache_flush, /* dcache_wbinv_all */
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(void *)arm3_cache_flush, /* dcache_wbinv_range */
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(void *)arm3_cache_flush, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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arm3_cache_flush, /* cache_purgeID s*/
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(void *)arm3_cache_flush, /* cache_purgeID_E s*/
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arm3_cache_flush, /* cache_purgeD s*/
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(void *)arm3_cache_flush, /* cache_purgeD_E s*/
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arm3_cache_flush, /* idcache_wbinv_all */
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(void *)arm3_cache_flush, /* idcache_wbinv_range */
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/* Other functions */
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@ -133,13 +127,6 @@ struct cpu_functions arm3_cpufuncs = {
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/* Soft functions */
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cpufunc_nullop, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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(void *)arm3_cache_flush, /* cache_purgeID_rng */
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(void *)arm3_cache_flush, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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early_abort_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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@ -174,24 +161,18 @@ struct cpu_functions arm6_cpufuncs = {
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arm67_tlb_flush, /* tlb_flushD */
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arm67_tlb_purge, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm67_cache_flush, /* cache_flushID */
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(void *)arm67_cache_flush, /* cache_flushID_SE */
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arm67_cache_flush, /* cache_flushI */
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(void *)arm67_cache_flush, /* cache_flushI_SE */
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arm67_cache_flush, /* cache_flushD */
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(void *)arm67_cache_flush, /* cache_flushD_SE */
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cpufunc_nullop, /* icache_sync_all */
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(void *) cpufunc_nullop, /* icache_sync_range */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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arm67_cache_flush, /* dcache_wbinv_all */
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(void *)arm67_cache_flush, /* dcache_wbinv_range */
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(void *)arm67_cache_flush, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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arm67_cache_flush, /* cache_purgeID s*/
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(void *)arm67_cache_flush, /* cache_purgeID_E s*/
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arm67_cache_flush, /* cache_purgeD s*/
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(void *)arm67_cache_flush, /* cache_purgeD_E s*/
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arm67_cache_flush, /* idcache_wbinv_all */
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(void *)arm67_cache_flush, /* idcache_wbinv_range */
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/* Other functions */
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@ -204,13 +185,6 @@ struct cpu_functions arm6_cpufuncs = {
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/* Soft functions */
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cpufunc_nullop, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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(void *)arm67_cache_flush, /* cache_purgeID_rng */
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(void *)arm67_cache_flush, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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#ifdef ARM6_LATE_ABORT
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late_abort_fixup, /* dataabt_fixup */
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#else
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@ -249,24 +223,18 @@ struct cpu_functions arm7_cpufuncs = {
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arm67_tlb_flush, /* tlb_flushD */
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arm67_tlb_purge, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm67_cache_flush, /* cache_flushID */
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(void *)arm67_cache_flush, /* cache_flushID_SE */
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arm67_cache_flush, /* cache_flushI */
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(void *)arm67_cache_flush, /* cache_flushI_SE */
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arm67_cache_flush, /* cache_flushD */
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(void *)arm67_cache_flush, /* cache_flushD_SE */
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cpufunc_nullop, /* icache_sync_all */
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(void *)cpufunc_nullop, /* icache_sync_range */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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arm67_cache_flush, /* dcache_wbinv_all */
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(void *)arm67_cache_flush, /* dcache_wbinv_range */
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(void *)arm67_cache_flush, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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arm67_cache_flush, /* cache_purgeID s*/
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(void *)arm67_cache_flush, /* cache_purgeID_E s*/
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arm67_cache_flush, /* cache_purgeD s*/
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(void *)arm67_cache_flush, /* cache_purgeD_E s*/
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arm67_cache_flush, /* idcache_wbinv_all */
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(void *)arm67_cache_flush, /* idcache_wbinv_range */
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/* Other functions */
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@ -279,13 +247,6 @@ struct cpu_functions arm7_cpufuncs = {
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/* Soft functions */
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cpufunc_nullop, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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(void *)arm67_cache_flush, /* cache_purgeID_rng */
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(void *)arm67_cache_flush, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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late_abort_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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@ -320,24 +281,18 @@ struct cpu_functions arm7tdmi_cpufuncs = {
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arm7tdmi_tlb_flushID, /* tlb_flushD */
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arm7tdmi_tlb_flushID_SE, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm7tdmi_cache_flushID, /* cache_flushID */
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(void *)arm7tdmi_cache_flushID, /* cache_flushID_SE */
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arm7tdmi_cache_flushID, /* cache_flushI */
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(void *)arm7tdmi_cache_flushID, /* cache_flushI_SE */
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arm7tdmi_cache_flushID, /* cache_flushD */
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(void *)arm7tdmi_cache_flushID, /* cache_flushD_SE */
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cpufunc_nullop, /* icache_sync_all */
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(void *)cpufunc_nullop, /* icache_sync_range */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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arm7tdmi_cache_flushID, /* dcache_wbinv_all */
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(void *)arm7tdmi_cache_flushID, /* dcache_wbinv_range */
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(void *)arm7tdmi_cache_flushID, /* dcache_inv_range */
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(void *)cpufunc_nullop, /* dcache_wb_range */
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arm7tdmi_cache_flushID, /* cache_purgeID s*/
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(void *)arm7tdmi_cache_flushID, /* cache_purgeID_E s*/
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arm7tdmi_cache_flushID, /* cache_purgeD s*/
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(void *)arm7tdmi_cache_flushID, /* cache_purgeD_E s*/
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arm7tdmi_cache_flushID, /* idcache_wbinv_all */
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(void *)arm7tdmi_cache_flushID, /* idcache_wbinv_range */
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/* Other functions */
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@ -350,13 +305,6 @@ struct cpu_functions arm7tdmi_cpufuncs = {
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/* Soft functions */
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cpufunc_nullop, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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(void *)arm7tdmi_cache_flushID, /* cache_purgeID_rng */
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(void *)arm7tdmi_cache_flushID, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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late_abort_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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@ -391,24 +339,18 @@ struct cpu_functions arm8_cpufuncs = {
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arm8_tlb_flushID, /* tlb_flushD */
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arm8_tlb_flushID_SE, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm8_cache_flushID, /* cache_flushID */
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arm8_cache_flushID_E, /* cache_flushID_SE */
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arm8_cache_flushID, /* cache_flushI */
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arm8_cache_flushID_E, /* cache_flushI_SE */
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arm8_cache_flushID, /* cache_flushD */
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arm8_cache_flushID_E, /* cache_flushD_SE */
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cpufunc_nullop, /* icache_sync_all */
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(void *)cpufunc_nullop, /* icache_sync_range */
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arm8_cache_cleanID, /* cache_cleanID s*/
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arm8_cache_cleanID_E, /* cache_cleanID_E s*/
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arm8_cache_cleanID, /* cache_cleanD s*/
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arm8_cache_cleanID_E, /* cache_cleanD_E */
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arm8_cache_purgeID, /* dcache_wbinv_all */
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(void *)arm8_cache_purgeID, /* dcache_wbinv_range */
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/*XXX*/ (void *)arm8_cache_purgeID, /* dcache_inv_range */
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(void *)arm8_cache_cleanID, /* dcache_wb_range */
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arm8_cache_purgeID, /* cache_purgeID s*/
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arm8_cache_purgeID_E, /* cache_purgeID_E s*/
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arm8_cache_purgeID, /* cache_purgeD s*/
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arm8_cache_purgeID_E, /* cache_purgeD_E s*/
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arm8_cache_purgeID, /* idcache_wbinv_all */
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(void *)arm8_cache_purgeID, /* idcache_wbinv_range */
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/* Other functions */
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@ -421,13 +363,6 @@ struct cpu_functions arm8_cpufuncs = {
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/* Soft functions */
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(void *)cpufunc_nullop, /* cache_syncI */
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(void *)arm8_cache_cleanID, /* cache_cleanID_rng */
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(void *)arm8_cache_cleanID, /* cache_cleanD_rng */
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(void *)arm8_cache_purgeID, /* cache_purgeID_rng */
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(void *)arm8_cache_purgeID, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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cpufunc_null_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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@ -461,25 +396,19 @@ struct cpu_functions arm9_cpufuncs = {
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armv4_tlb_flushD, /* tlb_flushD */
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armv4_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache functions */
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/* Cache operations */
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arm9_cache_flushID, /* cache_flushID */
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arm9_cache_flushID_SE, /* cache_flushID_SE */
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arm9_cache_flushI, /* cache_flushI */
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arm9_cache_flushI_SE, /* cache_flushI_SE */
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arm9_cache_flushD, /* cache_flushD */
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arm9_cache_flushD_SE, /* cache_flushD_SE */
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arm9_cache_syncI, /* icache_sync_all */
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arm9_cache_syncI_rng, /* icache_sync_range */
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/* ... lets use the cache in write-through mode. */
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arm9_cache_cleanID, /* cache_cleanID */
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(void *)arm9_cache_cleanID, /* cache_cleanID_SE */
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arm9_cache_cleanID, /* cache_cleanD */
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(void *)arm9_cache_cleanID, /* cache_cleanD_SE */
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/* ...cache in write-though mode... */
|
||||
arm9_cache_flushD, /* dcache_wbinv_all */
|
||||
arm9_cache_flushD_rng, /* dcache_wbinv_range */
|
||||
arm9_cache_flushD_rng, /* dcache_inv_range */
|
||||
(void *)cpufunc_nullop, /* dcache_wb_range */
|
||||
|
||||
arm9_cache_flushID, /* cache_purgeID */
|
||||
arm9_cache_flushID_SE, /* cache_purgeID_SE */
|
||||
arm9_cache_flushD, /* cache_purgeD */
|
||||
arm9_cache_flushD_SE, /* cache_purgeD_SE */
|
||||
arm9_cache_flushID, /* idcache_wbinv_all */
|
||||
arm9_cache_flushID_rng, /* idcache_wbinv_range */
|
||||
|
||||
/* Other functions */
|
||||
|
||||
@ -491,12 +420,6 @@ struct cpu_functions arm9_cpufuncs = {
|
||||
(void *)cpufunc_nullop, /* sleep */
|
||||
|
||||
/* Soft functions */
|
||||
arm9_cache_syncI, /* cache_syncI */
|
||||
(void *)arm9_cache_cleanID, /* cache_cleanID_rng */
|
||||
(void *)arm9_cache_cleanID, /* cache_cleanD_rng */
|
||||
arm9_cache_flushID_rng, /* cache_purgeID_rng */
|
||||
arm9_cache_flushD_rng, /* cache_purgeD_rng */
|
||||
arm9_cache_syncI_rng, /* cache_syncI_rng */
|
||||
|
||||
cpufunc_null_fixup, /* dataabt_fixup */
|
||||
cpufunc_null_fixup, /* prefetchabt_fixup */
|
||||
@ -532,24 +455,18 @@ struct cpu_functions sa110_cpufuncs = {
|
||||
armv4_tlb_flushD, /* tlb_flushD */
|
||||
armv4_tlb_flushD_SE, /* tlb_flushD_SE */
|
||||
|
||||
/* Cache functions */
|
||||
/* Cache operations */
|
||||
|
||||
sa110_cache_flushID, /* cache_flushID */
|
||||
(void *)sa110_cache_flushID, /* cache_flushID_SE */
|
||||
sa110_cache_flushI, /* cache_flushI */
|
||||
(void *)sa110_cache_flushI, /* cache_flushI_SE */
|
||||
sa110_cache_flushD, /* cache_flushD */
|
||||
sa110_cache_flushD_SE, /* cache_flushD_SE */
|
||||
sa110_cache_syncI, /* icache_sync_all */
|
||||
sa110_cache_syncI_rng, /* icache_sync_range */
|
||||
|
||||
sa110_cache_cleanID, /* cache_cleanID s*/
|
||||
sa110_cache_cleanD_E, /* cache_cleanID_E s*/
|
||||
sa110_cache_cleanD, /* cache_cleanD s*/
|
||||
sa110_cache_cleanD_E, /* cache_cleanD_E */
|
||||
sa110_cache_purgeD, /* dcache_wbinv_all */
|
||||
sa110_cache_purgeD_rng, /* dcache_wbinv_range */
|
||||
/*XXX*/ sa110_cache_purgeD_rng, /* dcache_inv_range */
|
||||
sa110_cache_cleanD_rng, /* dcache_wb_range */
|
||||
|
||||
sa110_cache_purgeID, /* cache_purgeID s*/
|
||||
sa110_cache_purgeID_E, /* cache_purgeID_E s*/
|
||||
sa110_cache_purgeD, /* cache_purgeD s*/
|
||||
sa110_cache_purgeD_E, /* cache_purgeD_E s*/
|
||||
sa110_cache_purgeID, /* idcache_wbinv_all */
|
||||
sa110_cache_purgeID_rng, /* idcache_wbinv_range */
|
||||
|
||||
/* Other functions */
|
||||
|
||||
@ -562,13 +479,6 @@ struct cpu_functions sa110_cpufuncs = {
|
||||
|
||||
/* Soft functions */
|
||||
|
||||
sa110_cache_syncI, /* cache_syncI */
|
||||
sa110_cache_cleanID_rng, /* cache_cleanID_rng */
|
||||
sa110_cache_cleanD_rng, /* cache_cleanD_rng */
|
||||
sa110_cache_purgeID_rng, /* cache_purgeID_rng */
|
||||
sa110_cache_purgeD_rng, /* cache_purgeD_rng */
|
||||
sa110_cache_syncI_rng, /* cache_syncI_rng */
|
||||
|
||||
cpufunc_null_fixup, /* dataabt_fixup */
|
||||
cpufunc_null_fixup, /* prefetchabt_fixup */
|
||||
|
||||
@ -602,24 +512,18 @@ struct cpu_functions xscale_cpufuncs = {
|
||||
armv4_tlb_flushD, /* tlb_flushD */
|
||||
armv4_tlb_flushD_SE, /* tlb_flushD_SE */
|
||||
|
||||
/* Cache functions */
|
||||
/* Cache operations */
|
||||
|
||||
xscale_cache_flushID, /* cache_flushID */
|
||||
(void *)xscale_cache_flushID, /* cache_flushID_SE */
|
||||
xscale_cache_flushI, /* cache_flushI */
|
||||
(void *)xscale_cache_flushI, /* cache_flushI_SE */
|
||||
xscale_cache_flushD, /* cache_flushD */
|
||||
xscale_cache_flushD_SE, /* cache_flushD_SE */
|
||||
xscale_cache_syncI, /* icache_sync_all */
|
||||
xscale_cache_syncI_rng, /* icache_sync_range */
|
||||
|
||||
xscale_cache_cleanID, /* cache_cleanID s*/
|
||||
xscale_cache_cleanD_E, /* cache_cleanID_E s*/
|
||||
xscale_cache_cleanD, /* cache_cleanD s*/
|
||||
xscale_cache_cleanD_E, /* cache_cleanD_E */
|
||||
xscale_cache_purgeD, /* dcache_wbinv_all */
|
||||
xscale_cache_purgeD_rng, /* dcache_wbinv_range */
|
||||
/*XXX*/ xscale_cache_purgeD_rng, /* dcache_inv_range */
|
||||
xscale_cache_cleanD_rng, /* dcache_wb_range */
|
||||
|
||||
xscale_cache_purgeID, /* cache_purgeID s*/
|
||||
xscale_cache_purgeID_E, /* cache_purgeID_E s*/
|
||||
xscale_cache_purgeD, /* cache_purgeD s*/
|
||||
xscale_cache_purgeD_E, /* cache_purgeD_E s*/
|
||||
xscale_cache_purgeID, /* idcache_wbinv_all */
|
||||
xscale_cache_purgeID_rng, /* idcache_wbinv_range */
|
||||
|
||||
/* Other functions */
|
||||
|
||||
@ -632,81 +536,6 @@ struct cpu_functions xscale_cpufuncs = {
|
||||
|
||||
/* Soft functions */
|
||||
|
||||
xscale_cache_syncI, /* cache_syncI */
|
||||
xscale_cache_cleanID_rng, /* cache_cleanID_rng */
|
||||
xscale_cache_cleanD_rng, /* cache_cleanD_rng */
|
||||
xscale_cache_purgeID_rng, /* cache_purgeID_rng */
|
||||
xscale_cache_purgeD_rng, /* cache_purgeD_rng */
|
||||
xscale_cache_syncI_rng, /* cache_syncI_rng */
|
||||
|
||||
cpufunc_null_fixup, /* dataabt_fixup */
|
||||
cpufunc_null_fixup, /* prefetchabt_fixup */
|
||||
|
||||
xscale_context_switch, /* context_switch */
|
||||
|
||||
xscale_setup /* cpu setup */
|
||||
};
|
||||
|
||||
struct cpu_functions xscale_writethrough_cpufuncs = {
|
||||
/* CPU functions */
|
||||
|
||||
cpufunc_id, /* id */
|
||||
xscale_cpwait, /* cpwait */
|
||||
|
||||
/* MMU functions */
|
||||
|
||||
xscale_control, /* control */
|
||||
cpufunc_domains, /* domain */
|
||||
xscale_setttb, /* setttb */
|
||||
cpufunc_faultstatus, /* faultstatus */
|
||||
cpufunc_faultaddress, /* faultaddress */
|
||||
|
||||
/* TLB functions */
|
||||
|
||||
armv4_tlb_flushID, /* tlb_flushID */
|
||||
xscale_tlb_flushID_SE, /* tlb_flushID_SE */
|
||||
armv4_tlb_flushI, /* tlb_flushI */
|
||||
(void *)armv4_tlb_flushI, /* tlb_flushI_SE */
|
||||
armv4_tlb_flushD, /* tlb_flushD */
|
||||
armv4_tlb_flushD_SE, /* tlb_flushD_SE */
|
||||
|
||||
/* Cache functions */
|
||||
|
||||
xscale_cache_flushID, /* cache_flushID */
|
||||
(void *)xscale_cache_flushID, /* cache_flushID_SE */
|
||||
xscale_cache_flushI, /* cache_flushI */
|
||||
(void *)xscale_cache_flushI, /* cache_flushI_SE */
|
||||
xscale_cache_flushD, /* cache_flushD */
|
||||
xscale_cache_flushD_SE, /* cache_flushD_SE */
|
||||
|
||||
cpufunc_nullop, /* cache_cleanID s*/
|
||||
(void *)cpufunc_nullop, /* cache_cleanID_E s*/
|
||||
cpufunc_nullop, /* cache_cleanD s*/
|
||||
(void *)cpufunc_nullop, /* cache_cleanD_E */
|
||||
|
||||
xscale_cache_flushID, /* cache_purgeID s*/
|
||||
(void *)xscale_cache_flushID, /* cache_purgeID_E s*/
|
||||
xscale_cache_flushD, /* cache_purgeD s*/
|
||||
xscale_cache_flushD_SE, /* cache_purgeD_E s*/
|
||||
|
||||
/* Other functions */
|
||||
|
||||
cpufunc_nullop, /* flush_prefetchbuf */
|
||||
armv4_drain_writebuf, /* drain_writebuf */
|
||||
cpufunc_nullop, /* flush_brnchtgt_C */
|
||||
(void *)cpufunc_nullop, /* flush_brnchtgt_E */
|
||||
|
||||
xscale_cpu_sleep, /* sleep */
|
||||
|
||||
/* Soft functions */
|
||||
|
||||
xscale_cache_flushI, /* cache_syncI */
|
||||
(void *)cpufunc_nullop, /* cache_cleanID_rng */
|
||||
(void *)cpufunc_nullop, /* cache_cleanD_rng */
|
||||
xscale_cache_flushID_rng, /* cache_purgeID_rng */
|
||||
xscale_cache_flushD_rng, /* cache_purgeD_rng */
|
||||
xscale_cache_flushI_rng, /* cache_syncI_rng */
|
||||
|
||||
cpufunc_null_fixup, /* dataabt_fixup */
|
||||
cpufunc_null_fixup, /* prefetchabt_fixup */
|
||||
|
||||
@ -907,7 +736,7 @@ set_cpufuncs()
|
||||
: "r" (BCUCTL_E0|BCUCTL_E1|BCUCTL_EV));
|
||||
|
||||
pte_cache_mode = PT_C; /* Select write-through cacheing. */
|
||||
cpufuncs = xscale_writethrough_cpufuncs;
|
||||
cpufuncs = xscale_cpufuncs;
|
||||
cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
|
||||
get_cachetype();
|
||||
return 0;
|
||||
@ -1411,7 +1240,7 @@ arm6_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, arm6_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
@ -1451,7 +1280,7 @@ arm7_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, arm7_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
@ -1483,7 +1312,7 @@ arm7tdmi_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
@ -1557,7 +1386,7 @@ arm8_setup(args)
|
||||
}
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
@ -1602,7 +1431,7 @@ arm9_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, arm9_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
cpu_control(0xffffffff, cpuctrl);
|
||||
@ -1648,7 +1477,7 @@ sa110_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, sa110_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Set the control register */
|
||||
/* cpu_control(cpuctrlmask, cpuctrl);*/
|
||||
@ -1705,7 +1534,7 @@ xscale_setup(args)
|
||||
cpuctrl = parse_cpu_options(args, xscale_options, cpuctrl);
|
||||
|
||||
/* Clear out the cache */
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/*
|
||||
* Set the control register. Note that bits 6:3 must always
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: fiq.c,v 1.2 2001/12/20 16:12:10 bjh21 Exp $ */
|
||||
/* $NetBSD: fiq.c,v 1.3 2002/01/25 19:19:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Wasabi Systems, Inc.
|
||||
@ -36,7 +36,7 @@
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.2 2001/12/20 16:12:10 bjh21 Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: fiq.c,v 1.3 2002/01/25 19:19:24 thorpej Exp $");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
@ -77,7 +77,7 @@ fiq_installhandler(void *func, size_t size)
|
||||
|
||||
#ifdef __PROG32
|
||||
zero_page_readonly();
|
||||
cpu_cache_syncI_rng((vaddr_t) fiqvector, size);
|
||||
cpu_icache_sync_range((vaddr_t) fiqvector, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: sig_machdep.c,v 1.9 2001/11/23 19:21:47 thorpej Exp $ */
|
||||
/* $NetBSD: sig_machdep.c,v 1.10 2002/01/25 19:19:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
||||
@ -44,7 +44,7 @@
|
||||
|
||||
#include <sys/param.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: sig_machdep.c,v 1.9 2001/11/23 19:21:47 thorpej Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: sig_machdep.c,v 1.10 2002/01/25 19:19:24 thorpej Exp $");
|
||||
|
||||
#include <sys/mount.h> /* XXX only needed by syscallargs.h */
|
||||
#include <sys/proc.h>
|
||||
@ -163,7 +163,8 @@ sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
|
||||
tf->tf_usr_sp = (int)fp;
|
||||
tf->tf_pc = (int)p->p_sigctx.ps_sigcode;
|
||||
#ifndef arm26
|
||||
cpu_cache_syncI();
|
||||
/* XXX This should not be needed. */
|
||||
cpu_icache_sync_all();
|
||||
#endif
|
||||
|
||||
/* Remember that we're now on the signal stack. */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: bus_dma.c,v 1.5 2001/11/26 20:49:04 thorpej Exp $ */
|
||||
/* $NetBSD: bus_dma.c,v 1.6 2002/01/25 19:19:24 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
|
||||
@ -383,7 +383,7 @@ _bus_dmamap_sync(t, map, offset, len, ops)
|
||||
printf("syncing: %lx,%lx\n", vaddr, length);
|
||||
#endif /* DEBUG_DMA */
|
||||
/* Actually sync the cache */
|
||||
cpu_cache_purgeD_rng(vaddr, length);
|
||||
cpu_dcache_wbinv_range(vaddr, length);
|
||||
|
||||
/* Adjust the length */
|
||||
len -= length;
|
||||
@ -522,7 +522,7 @@ _bus_dmamem_map(t, segs, nsegs, size, kvap, flags)
|
||||
* uncacheable.
|
||||
*/
|
||||
if (flags & BUS_DMA_COHERENT) {
|
||||
cpu_cache_purgeD_rng(va, NBPG);
|
||||
cpu_dcache_wbinv_range(va, NBPG);
|
||||
cpu_drain_writebuf();
|
||||
ptep = vtopte(va);
|
||||
*ptep = ((*ptep) & (~PT_C | PT_B));
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cpuswitch.S,v 1.5 2001/11/29 17:14:02 thorpej Exp $ */
|
||||
/* $NetBSD: cpuswitch.S,v 1.6 2002/01/25 19:19:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
||||
@ -496,7 +496,7 @@ switch_exited:
|
||||
stmfd sp!, {r0-r3}
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lcs_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lcs_cache_purged:
|
||||
ldmfd sp!, {r0-r3}
|
||||
@ -593,7 +593,7 @@ ENTRY(switch_exit)
|
||||
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lse_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lse_cache_purged:
|
||||
ldmfd sp!, {r0-r3}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: db_interface.c,v 1.16 2002/01/17 23:56:01 thorpej Exp $ */
|
||||
/* $NetBSD: db_interface.c,v 1.17 2002/01/25 19:19:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1996 Scott K. Stevens
|
||||
@ -270,7 +270,7 @@ db_write_text(vaddr_t addr, size_t size, char *data)
|
||||
} while (size != 0);
|
||||
|
||||
/* Sync the I-cache. */
|
||||
cpu_cache_syncI_rng(addr, savesize);
|
||||
cpu_icache_sync_range(addr, savesize);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -299,7 +299,7 @@ db_write_bytes(vaddr_t addr, size_t size, char *data)
|
||||
*dst++ = *data++;
|
||||
}
|
||||
/* make sure the caches and memory are in sync */
|
||||
cpu_cache_syncI_rng(addr, size);
|
||||
cpu_icache_sync_range(addr, size);
|
||||
|
||||
/* In case the current page tables have been modified ... */
|
||||
cpu_tlb_flushID();
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
# $NetBSD: genassym.cf,v 1.8 2001/12/20 01:20:22 thorpej Exp $
|
||||
# $NetBSD: genassym.cf,v 1.9 2002/01/25 19:19:25 thorpej Exp $
|
||||
|
||||
# Copyright (c) 1982, 1990 The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
@ -117,7 +117,7 @@ define TF_PC offsetof(struct trapframe, tf_pc)
|
||||
define PROCSIZE sizeof(struct proc)
|
||||
define TRAPFRAMESIZE sizeof(struct trapframe)
|
||||
|
||||
define CF_CACHE_PURGE_ID offsetof(struct cpu_functions, cf_cache_purgeID)
|
||||
define CF_IDCACHE_WBINV_ALL offsetof(struct cpu_functions, cf_idcache_wbinv_all)
|
||||
define CF_CONTEXT_SWITCH offsetof(struct cpu_functions, cf_context_switch)
|
||||
define CF_SLEEP offsetof(struct cpu_functions, cf_sleep)
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore.S,v 1.2 2001/12/20 01:20:22 thorpej Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.3 2002/01/25 19:19:25 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1994-1997 Mark Brinicombe
|
||||
@ -123,7 +123,7 @@ ENTRY_NP(cpu_reset)
|
||||
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lboot_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lboot_cache_purged:
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: pmap.c,v 1.35 2002/01/20 03:41:48 thorpej Exp $ */
|
||||
/* $NetBSD: pmap.c,v 1.36 2002/01/25 19:19:25 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Richard Earnshaw
|
||||
@ -142,7 +142,7 @@
|
||||
#include <machine/param.h>
|
||||
#include <arm/arm32/katelib.h>
|
||||
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.35 2002/01/20 03:41:48 thorpej Exp $");
|
||||
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.36 2002/01/25 19:19:25 thorpej Exp $");
|
||||
#ifdef PMAP_DEBUG
|
||||
#define PDEBUG(_lev_,_stat_) \
|
||||
if (pmap_debug_level >= (_lev_)) \
|
||||
@ -1172,7 +1172,7 @@ pmap_bootstrap(kernel_l1pt, kernel_ptpt)
|
||||
pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl",
|
||||
0, pool_page_alloc_nointr, pool_page_free_nointr, M_VMPMAP);
|
||||
|
||||
cpu_cache_cleanD();
|
||||
cpu_dcache_wbinv_all();
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1827,9 +1827,9 @@ pmap_clean_page(pv, is_src)
|
||||
}
|
||||
|
||||
if (page_to_clean)
|
||||
cpu_cache_purgeID_rng(page_to_clean, NBPG);
|
||||
cpu_idcache_wbinv_range(page_to_clean, NBPG);
|
||||
else if (cache_needs_cleaning) {
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
return (1);
|
||||
}
|
||||
return (0);
|
||||
@ -1882,7 +1882,7 @@ pmap_zero_page(phys)
|
||||
cpu_tlb_flushD_SE(page_hook0.va);
|
||||
cpu_cpwait();
|
||||
bzero_page(page_hook0.va);
|
||||
cpu_cache_purgeD_rng(page_hook0.va, NBPG);
|
||||
cpu_dcache_wbinv_range(page_hook0.va, NBPG);
|
||||
}
|
||||
|
||||
/* pmap_pageidlezero()
|
||||
@ -1934,7 +1934,7 @@ pmap_pageidlezero(phys)
|
||||
* if we aborted we'll rezero this page again later so don't
|
||||
* purge it unless we finished it
|
||||
*/
|
||||
cpu_cache_purgeD_rng(page_hook0.va, NBPG);
|
||||
cpu_dcache_wbinv_range(page_hook0.va, NBPG);
|
||||
return (rv);
|
||||
}
|
||||
|
||||
@ -1977,8 +1977,8 @@ pmap_copy_page(src, dest)
|
||||
cpu_tlb_flushD_SE(page_hook1.va);
|
||||
cpu_cpwait();
|
||||
bcopy_page(page_hook0.va, page_hook1.va);
|
||||
cpu_cache_purgeD_rng(page_hook0.va, NBPG);
|
||||
cpu_cache_purgeD_rng(page_hook1.va, NBPG);
|
||||
cpu_dcache_wbinv_range(page_hook0.va, NBPG);
|
||||
cpu_dcache_wbinv_range(page_hook1.va, NBPG);
|
||||
}
|
||||
|
||||
#if 0
|
||||
@ -2252,7 +2252,7 @@ pmap_vac_me_user(struct pmap *pmap, struct pv_head *pvh, pt_entry_t *ptes,
|
||||
(clear_cache || npv->pv_pmap == kpmap)) ||
|
||||
(npv->pv_pmap == kpmap &&
|
||||
!clear_cache && kern_cacheable < 4)) {
|
||||
cpu_cache_purgeID_rng(npv->pv_va,
|
||||
cpu_idcache_wbinv_range(npv->pv_va,
|
||||
NBPG);
|
||||
cpu_tlb_flushID_SE(npv->pv_va);
|
||||
}
|
||||
@ -2260,7 +2260,7 @@ pmap_vac_me_user(struct pmap *pmap, struct pv_head *pvh, pt_entry_t *ptes,
|
||||
}
|
||||
if ((clear_cache && cacheable_entries >= 4) ||
|
||||
kern_cacheable >= 4) {
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
cpu_tlb_flushID();
|
||||
}
|
||||
cpu_cpwait();
|
||||
@ -2387,7 +2387,7 @@ pmap_remove(pmap, sva, eva)
|
||||
|
||||
/* Nuke everything if needed. */
|
||||
if (pmap_active) {
|
||||
cpu_cache_purgeID();
|
||||
cpu_idcache_wbinv_all();
|
||||
cpu_tlb_flushID();
|
||||
}
|
||||
|
||||
@ -2441,7 +2441,8 @@ pmap_remove(pmap, sva, eva)
|
||||
|
||||
for (cnt = 0; cnt < cleanlist_idx; cnt++) {
|
||||
if (pmap_active) {
|
||||
cpu_cache_purgeID_rng(cleanlist[cnt].va, NBPG);
|
||||
cpu_idcache_wbinv_range(cleanlist[cnt].va,
|
||||
NBPG);
|
||||
*cleanlist[cnt].pte = 0;
|
||||
cpu_tlb_flushID_SE(cleanlist[cnt].va);
|
||||
} else
|
||||
@ -2756,7 +2757,7 @@ pmap_enter(pmap, va, pa, prot, flags)
|
||||
}
|
||||
} else {
|
||||
/* We are replacing the page with a new one. */
|
||||
cpu_cache_purgeID_rng(va, NBPG);
|
||||
cpu_idcache_wbinv_range(va, NBPG);
|
||||
|
||||
PDEBUG(0, printf("Case 03 in pmap_enter (V%08lx P%08lx P%08lx)\n",
|
||||
va, pa, opa));
|
||||
@ -2938,7 +2939,7 @@ pmap_kremove(va, len)
|
||||
|
||||
KASSERT(pmap_pde_page(pmap_pde(pmap_kernel(), va)));
|
||||
pte = vtopte(va);
|
||||
cpu_cache_purgeID_rng(va, PAGE_SIZE);
|
||||
cpu_idcache_wbinv_range(va, PAGE_SIZE);
|
||||
*pte = 0;
|
||||
cpu_tlb_flushID_SE(va);
|
||||
}
|
||||
@ -3383,7 +3384,7 @@ pmap_clearbit(pa, maskbits)
|
||||
* current if it is flush it,
|
||||
* otherwise it won't be in the cache
|
||||
*/
|
||||
cpu_cache_purgeID_rng(pv->pv_va, NBPG);
|
||||
cpu_idcache_wbinv_range(pv->pv_va, NBPG);
|
||||
|
||||
/* make the pte read only */
|
||||
*pte &= ~PT_AP(AP_W);
|
||||
@ -3630,7 +3631,7 @@ pmap_procwr(p, va, len)
|
||||
{
|
||||
/* We only need to do anything if it is the current process. */
|
||||
if (p == curproc)
|
||||
cpu_cache_syncI_rng(va, len);
|
||||
cpu_icache_sync_range(va, len);
|
||||
}
|
||||
/*
|
||||
* PTP functions
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: sys_machdep.c,v 1.2 2002/01/05 22:41:47 chris Exp $ */
|
||||
/* $NetBSD: sys_machdep.c,v 1.3 2002/01/25 19:19:25 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995-1997 Mark Brinicombe.
|
||||
@ -67,7 +67,7 @@ arm32_sync_icache(p, args, retval)
|
||||
if ((error = copyin(args, &ua, sizeof(ua))) != 0)
|
||||
return (error);
|
||||
|
||||
cpu_cache_syncI_rng(ua.addr, ua.len);
|
||||
cpu_icache_sync_range(ua.addr, ua.len);
|
||||
|
||||
*retval = 0;
|
||||
return(0);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: vm_machdep.c,v 1.11 2001/11/29 17:12:22 thorpej Exp $ */
|
||||
/* $NetBSD: vm_machdep.c,v 1.12 2002/01/25 19:19:25 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
||||
@ -300,7 +300,7 @@ pagemove(from, to, size)
|
||||
* the 'from' area.
|
||||
*/
|
||||
|
||||
cpu_cache_purgeD_rng((u_int)from, size);
|
||||
cpu_dcache_wbinv_range((vaddr_t) from, size);
|
||||
|
||||
while (size > 0) {
|
||||
*tpte++ = *fpte;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cpufunc.h,v 1.16 2002/01/24 04:23:19 briggs Exp $ */
|
||||
/* $NetBSD: cpufunc.h,v 1.17 2002/01/25 19:19:26 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Mark Brinicombe.
|
||||
@ -73,24 +73,66 @@ struct cpu_functions {
|
||||
void (*cf_tlb_flushD) __P((void));
|
||||
void (*cf_tlb_flushD_SE) __P((u_int va));
|
||||
|
||||
/* Cache functions */
|
||||
/*
|
||||
* Cache operations:
|
||||
*
|
||||
* We define the following primitives:
|
||||
*
|
||||
* icache_sync_all Synchronize I-cache
|
||||
* icache_sync_range Synchronize I-cache range
|
||||
*
|
||||
* dcache_wbinv_all Write-back and Invalidate D-cache
|
||||
* dcache_wbinv_range Write-back and Invalidate D-cache range
|
||||
* dcache_inv_range Invalidate D-cache range
|
||||
* dcache_wb_range Write-back D-cache range
|
||||
*
|
||||
* idcache_wbinv_all Write-back and Invalidate D-cache,
|
||||
* Invalidate I-cache
|
||||
* idcache_wbinv_range Write-back and Invalidate D-cache,
|
||||
* Invalidate I-cache range
|
||||
*
|
||||
* Note that the ARM term for "write-back" is "clean". We use
|
||||
* the term "write-back" since it's a more common way to describe
|
||||
* the operation.
|
||||
*
|
||||
* There are some rules that must be followed:
|
||||
*
|
||||
* I-cache Synch (all or range):
|
||||
* The goal is to synchronize the instruction stream,
|
||||
* so you may beed to write-back dirty D-cache blocks
|
||||
* first. If a range is requested, and you can't
|
||||
* synchronize just a range, you have to hit the whole
|
||||
* thing.
|
||||
*
|
||||
* D-cache Write-Back and Invalidate range:
|
||||
* If you can't WB-Inv a range, you must WB-Inv the
|
||||
* entire D-cache.
|
||||
*
|
||||
* D-cache Invalidate:
|
||||
* If you can't Inv the D-cache, you must Write-Back
|
||||
* and Invalidate. Code that uses this operation
|
||||
* MUST NOT assume that the D-cache will not be written
|
||||
* back to memory.
|
||||
*
|
||||
* D-cache Write-Back:
|
||||
* If you can't Write-back without doing an Inv,
|
||||
* that's fine. Then treat this as a WB-Inv.
|
||||
* Skipping the invalidate is merely an optimization.
|
||||
*
|
||||
* All operations:
|
||||
* Valid virtual addresses must be passed to each
|
||||
* cache operation.
|
||||
*/
|
||||
void (*cf_icache_sync_all) __P((void));
|
||||
void (*cf_icache_sync_range) __P((vaddr_t, vsize_t));
|
||||
|
||||
void (*cf_cache_flushID) __P((void));
|
||||
void (*cf_cache_flushID_SE) __P((u_int va));
|
||||
void (*cf_cache_flushI) __P((void));
|
||||
void (*cf_cache_flushI_SE) __P((u_int va));
|
||||
void (*cf_cache_flushD) __P((void));
|
||||
void (*cf_cache_flushD_SE) __P((u_int va));
|
||||
void (*cf_dcache_wbinv_all) __P((void));
|
||||
void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t));
|
||||
void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t));
|
||||
void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t));
|
||||
|
||||
void (*cf_cache_cleanID) __P((void));
|
||||
void (*cf_cache_cleanID_E) __P((u_int imp));
|
||||
void (*cf_cache_cleanD) __P((void));
|
||||
void (*cf_cache_cleanD_E) __P((u_int imp));
|
||||
|
||||
void (*cf_cache_purgeID) __P((void));
|
||||
void (*cf_cache_purgeID_E) __P((u_int imp));
|
||||
void (*cf_cache_purgeD) __P((void));
|
||||
void (*cf_cache_purgeD_E) __P((u_int imp));
|
||||
void (*cf_idcache_wbinv_all) __P((void));
|
||||
void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t));
|
||||
|
||||
/* Other functions */
|
||||
|
||||
@ -103,13 +145,6 @@ struct cpu_functions {
|
||||
|
||||
/* Soft functions */
|
||||
|
||||
void (*cf_cache_syncI) __P((void));
|
||||
void (*cf_cache_cleanID_rng) __P((u_int start, u_int len));
|
||||
void (*cf_cache_cleanD_rng) __P((u_int start, u_int len));
|
||||
void (*cf_cache_purgeID_rng) __P((u_int start, u_int len));
|
||||
void (*cf_cache_purgeD_rng) __P((u_int start, u_int len));
|
||||
void (*cf_cache_syncI_rng) __P((u_int start, u_int len));
|
||||
|
||||
int (*cf_dataabt_fixup) __P((void *arg));
|
||||
int (*cf_prefetchabt_fixup) __P((void *arg));
|
||||
|
||||
@ -137,20 +172,16 @@ extern u_int cputype;
|
||||
#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
|
||||
#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
|
||||
|
||||
#define cpu_cache_flushID() cpufuncs.cf_cache_flushID()
|
||||
#define cpu_cache_flushID_SE(e) cpufuncs.cf_cache_flushID_SE(e)
|
||||
#define cpu_cache_flushI() cpufuncs.cf_cache_flushI()
|
||||
#define cpu_cache_flushI_SE(e) cpufuncs.cf_cache_flushI_SE(e)
|
||||
#define cpu_cache_flushD() cpufuncs.cf_cache_flushD()
|
||||
#define cpu_cache_flushD_SE(e) cpufuncs.cf_cache_flushD_SE(e)
|
||||
#define cpu_cache_cleanID() cpufuncs.cf_cache_cleanID()
|
||||
#define cpu_cache_cleanID_E(e) cpufuncs.cf_cache_cleanID_E(e)
|
||||
#define cpu_cache_cleanD() cpufuncs.cf_cache_cleanD()
|
||||
#define cpu_cache_cleanD_E(e) cpufuncs.cf_cache_cleanD_E(e)
|
||||
#define cpu_cache_purgeID() cpufuncs.cf_cache_purgeID()
|
||||
#define cpu_cache_purgeID_E(e) cpufuncs.cf_cache_purgeID_E(e)
|
||||
#define cpu_cache_purgeD() cpufuncs.cf_cache_purgeD()
|
||||
#define cpu_cache_purgeD_E(e) cpufuncs.cf_cache_purgeD_E(e)
|
||||
#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
|
||||
#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
|
||||
|
||||
#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
|
||||
#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
|
||||
#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
|
||||
#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
|
||||
|
||||
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
|
||||
#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
|
||||
|
||||
#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
|
||||
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
|
||||
@ -159,13 +190,6 @@ extern u_int cputype;
|
||||
|
||||
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
|
||||
|
||||
#define cpu_cache_syncI() cpufuncs.cf_cache_syncI()
|
||||
#define cpu_cache_cleanID_rng(s,l) cpufuncs.cf_cache_cleanID_rng(s,l)
|
||||
#define cpu_cache_cleanD_rng(s,l) cpufuncs.cf_cache_cleanD_rng(s,l)
|
||||
#define cpu_cache_purgeID_rng(s,l) cpufuncs.cf_cache_purgeID_rng(s,l)
|
||||
#define cpu_cache_purgeD_rng(s,l) cpufuncs.cf_cache_purgeD_rng(s,l)
|
||||
#define cpu_cache_syncI_rng(s,l) cpufuncs.cf_cache_syncI_rng(s,l)
|
||||
|
||||
#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
|
||||
#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
|
||||
#define ABORT_FIXUP_OK 0 /* fixup succeeded */
|
||||
@ -231,11 +255,11 @@ void arm8_cache_purgeID __P((void));
|
||||
void arm8_cache_purgeID_E __P((u_int entry));
|
||||
|
||||
void arm8_cache_syncI __P((void));
|
||||
void arm8_cache_cleanID_rng __P((u_int start, u_int end));
|
||||
void arm8_cache_cleanD_rng __P((u_int start, u_int end));
|
||||
void arm8_cache_purgeID_rng __P((u_int start, u_int end));
|
||||
void arm8_cache_purgeD_rng __P((u_int start, u_int end));
|
||||
void arm8_cache_syncI_rng __P((u_int start, u_int end));
|
||||
void arm8_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
|
||||
void arm8_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
|
||||
void arm8_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
|
||||
void arm8_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
|
||||
void arm8_cache_syncI_rng __P((vaddr_t start, vsize_t end));
|
||||
|
||||
void arm8_context_switch __P((void));
|
||||
|
||||
@ -259,9 +283,9 @@ void arm9_cache_flushD_SE __P((u_int));
|
||||
void arm9_cache_cleanID __P((void));
|
||||
|
||||
void arm9_cache_syncI __P((void));
|
||||
void arm9_cache_flushID_rng __P((u_int, u_int));
|
||||
void arm9_cache_flushD_rng __P((u_int, u_int));
|
||||
void arm9_cache_syncI_rng __P((u_int, u_int));
|
||||
void arm9_cache_flushID_rng __P((vaddr_t, vsize_t));
|
||||
void arm9_cache_flushD_rng __P((vaddr_t, vsize_t));
|
||||
void arm9_cache_syncI_rng __P((vaddr_t, vsize_t));
|
||||
|
||||
void arm9_context_switch __P((void));
|
||||
|
||||
@ -297,11 +321,11 @@ void sa110_cache_purgeD __P((void));
|
||||
void sa110_cache_purgeD_E __P((u_int entry));
|
||||
|
||||
void sa110_cache_syncI __P((void));
|
||||
void sa110_cache_cleanID_rng __P((u_int start, u_int end));
|
||||
void sa110_cache_cleanD_rng __P((u_int start, u_int end));
|
||||
void sa110_cache_purgeID_rng __P((u_int start, u_int end));
|
||||
void sa110_cache_purgeD_rng __P((u_int start, u_int end));
|
||||
void sa110_cache_syncI_rng __P((u_int start, u_int end));
|
||||
void sa110_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
|
||||
void sa110_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
|
||||
void sa110_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
|
||||
void sa110_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
|
||||
void sa110_cache_syncI_rng __P((vaddr_t start, vsize_t end));
|
||||
|
||||
void sa110_context_switch __P((void));
|
||||
|
||||
@ -334,16 +358,16 @@ void xscale_cache_purgeD __P((void));
|
||||
void xscale_cache_purgeD_E __P((u_int entry));
|
||||
|
||||
void xscale_cache_syncI __P((void));
|
||||
void xscale_cache_cleanID_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_cleanD_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_purgeID_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_purgeD_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_syncI_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_syncI_rng __P((vaddr_t start, vsize_t end));
|
||||
|
||||
/* Used in write-through mode. */
|
||||
void xscale_cache_flushID_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_flushD_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_flushI_rng __P((u_int start, u_int end));
|
||||
void xscale_cache_flushID_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_flushD_rng __P((vaddr_t start, vsize_t end));
|
||||
void xscale_cache_flushI_rng __P((vaddr_t start, vsize_t end));
|
||||
|
||||
void xscale_context_switch __P((void));
|
||||
|
||||
@ -352,9 +376,6 @@ void xscale_setup __P((char *string));
|
||||
|
||||
#define tlb_flush cpu_tlb_flushID
|
||||
#define setttb cpu_setttb
|
||||
#define cache_clean cpu_cache_purgeID
|
||||
#define sync_caches cpu_cache_syncI
|
||||
#define sync_icache cpu_cache_syncI
|
||||
#define drain_writebuf cpu_drain_writebuf
|
||||
|
||||
/*
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: iomd_dma.c,v 1.2 2001/11/27 01:03:52 thorpej Exp $ */
|
||||
/* $NetBSD: iomd_dma.c,v 1.3 2002/01/25 19:19:26 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995 Scott Stevens
|
||||
@ -218,7 +218,7 @@ fill:
|
||||
/*
|
||||
* Flush the cache for this address
|
||||
*/
|
||||
cpu_cache_purgeD_rng((vm_offset_t)dp->dc_nextaddr, len);
|
||||
cpu_dcache_wbinv_range((vm_offset_t)dp->dc_nextaddr, len);
|
||||
|
||||
dp->dc_nextaddr += len;
|
||||
dp->dc_len -= len;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ofw.c,v 1.29 2001/11/27 01:06:29 thorpej Exp $ */
|
||||
/* $NetBSD: ofw.c,v 1.30 2002/01/25 19:19:26 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -964,7 +964,7 @@ ofw_callbackhandler(args)
|
||||
}
|
||||
|
||||
/* Write-back anything stuck in the cache. */
|
||||
cache_clean();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Install new mappings. */
|
||||
{
|
||||
@ -1006,7 +1006,7 @@ ofw_callbackhandler(args)
|
||||
}
|
||||
|
||||
/* Write-back anything stuck in the cache. */
|
||||
cache_clean();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Zero the mappings. */
|
||||
{
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ofwgencfg_machdep.c,v 1.20 2001/11/27 01:06:30 thorpej Exp $ */
|
||||
/* $NetBSD: ofwgencfg_machdep.c,v 1.21 2002/01/25 19:19:27 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -202,7 +202,7 @@ initarm(ofw_handle)
|
||||
}
|
||||
|
||||
/* Sync the first 16 words of memory */
|
||||
cpu_cache_syncI_rng(0, 64);
|
||||
cpu_icache_sync_range(0, 64);
|
||||
}
|
||||
|
||||
data_abort_handler_address = (u_int)data_abort_handler;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: shark_machdep.c,v 1.29 2001/12/20 01:20:27 thorpej Exp $ */
|
||||
/* $NetBSD: shark_machdep.c,v 1.30 2002/01/25 19:19:27 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -284,7 +284,7 @@ initarm(ofw_handle)
|
||||
}
|
||||
|
||||
/* Sync the first 16 words of memory */
|
||||
cpu_cache_syncI_rng(0, 64);
|
||||
cpu_icache_sync_range(0, 64);
|
||||
}
|
||||
|
||||
data_abort_handler_address = (u_int)data_abort_handler;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cats_machdep.c,v 1.11 2002/01/22 19:14:48 chris Exp $ */
|
||||
/* $NetBSD: cats_machdep.c,v 1.12 2002/01/25 19:19:28 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997,1998 Mark Brinicombe.
|
||||
@ -673,7 +673,7 @@ initarm(bootargs)
|
||||
memcpy((char *)0x00000000, page0, page0_end - page0);
|
||||
|
||||
/* We have modified a text page so sync the icache */
|
||||
cpu_cache_syncI();
|
||||
cpu_icache_sync_all();
|
||||
|
||||
/*
|
||||
* Pages were allocated during the secondary bootstrap for the
|
||||
@ -782,38 +782,6 @@ process_kernel_args(args)
|
||||
parse_mi_bootargs(boot_args);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
arm32_cachectl(va, len, flags)
|
||||
vm_offset_t va;
|
||||
int len;
|
||||
int flags;
|
||||
{
|
||||
pt_entry_t *ptep, pte;
|
||||
int loop;
|
||||
vm_offset_t addr;
|
||||
|
||||
/* printf("arm32_cachectl(%x,%x,%x)\n", va, len, flags);*/
|
||||
|
||||
if (flags & 1) {
|
||||
addr = va;
|
||||
loop = len;
|
||||
while (loop > 0) {
|
||||
ptep = vtopte(addr & (~PGOFSET));
|
||||
pte = *ptep;
|
||||
|
||||
*ptep = (pte & ~(PT_C | PT_B)) | (flags & (PT_C | PT_B));
|
||||
|
||||
loop -= NBPG;
|
||||
addr += NBPG;
|
||||
}
|
||||
tlb_flush();
|
||||
}
|
||||
|
||||
cpu_cache_purgeD_rng(va, len);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern struct bus_space footbridge_pci_io_bs_tag;
|
||||
extern struct bus_space footbridge_pci_mem_bs_tag;
|
||||
void footbridge_pci_bs_tag_init __P((void));
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: dnard_machdep.c,v 1.8 2002/01/13 20:20:13 thorpej Exp $ */
|
||||
/* $NetBSD: dnard_machdep.c,v 1.9 2002/01/25 19:19:28 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -280,7 +280,7 @@ initarm(ofw_handle)
|
||||
}
|
||||
|
||||
/* Sync the first 16 words of memory */
|
||||
cpu_cache_syncI_rng(0, 64);
|
||||
cpu_icache_sync_range(0, 64);
|
||||
}
|
||||
|
||||
data_abort_handler_address = (u_int)data_abort_handler;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: ofw.c,v 1.4 2001/11/27 01:10:13 thorpej Exp $ */
|
||||
/* $NetBSD: ofw.c,v 1.5 2002/01/25 19:19:28 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 1997
|
||||
@ -774,7 +774,7 @@ ofw_configmem(void)
|
||||
/* First initialize our callback memory allocator. */
|
||||
ofw_initallocator();
|
||||
|
||||
OF_set_callback((void(*)())ofw_callbackhandler);
|
||||
OF_set_callback((void *) ofw_callbackhandler);
|
||||
|
||||
/* Switch to the proc0 pagetables. */
|
||||
setttb(proc0_ttbbase.pv_pa);
|
||||
@ -965,7 +965,7 @@ ofw_callbackhandler(args)
|
||||
}
|
||||
|
||||
/* Write-back anything stuck in the cache. */
|
||||
cache_clean();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Install new mappings. */
|
||||
{
|
||||
@ -1007,7 +1007,7 @@ ofw_callbackhandler(args)
|
||||
}
|
||||
|
||||
/* Write-back anything stuck in the cache. */
|
||||
cache_clean();
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Zero the mappings. */
|
||||
{
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: int_bus_dma.c,v 1.3 2001/11/26 20:49:05 thorpej Exp $ */
|
||||
/* $NetBSD: int_bus_dma.c,v 1.4 2002/01/25 19:19:29 thorpej Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
|
||||
@ -344,7 +344,7 @@ integrator_bus_dmamem_map(t, segs, nsegs, size, kvap, flags)
|
||||
* uncacheable.
|
||||
*/
|
||||
if (flags & BUS_DMA_COHERENT) {
|
||||
cpu_cache_purgeD_rng(va, NBPG);
|
||||
cpu_dcache_wbinv_range(va, NBPG);
|
||||
cpu_drain_writebuf();
|
||||
ptep = vtopte(va);
|
||||
*ptep = ((*ptep) & (~PT_C | PT_B));
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: integrator_machdep.c,v 1.6 2001/11/23 21:18:34 thorpej Exp $ */
|
||||
/* $NetBSD: integrator_machdep.c,v 1.7 2002/01/25 19:19:29 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 ARM Ltd
|
||||
@ -769,7 +769,7 @@ initarm(bootinfo)
|
||||
memcpy((char *)0x00000000, page0, page0_end - page0);
|
||||
|
||||
/* We have modified a text page so sync the icache */
|
||||
cpu_cache_syncI();
|
||||
cpu_icache_sync_all();
|
||||
|
||||
/*
|
||||
* Pages were allocated during the secondary bootstrap for the
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: iq80310_machdep.c,v 1.16 2002/01/20 03:41:48 thorpej Exp $ */
|
||||
/* $NetBSD: iq80310_machdep.c,v 1.17 2002/01/25 19:19:29 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
|
||||
@ -770,7 +770,7 @@ initarm(void *arg)
|
||||
memcpy((char *)0x00000000, page0, page0_end - page0);
|
||||
|
||||
/* We have modified a text page so sync the icache */
|
||||
cpu_cache_syncI();
|
||||
cpu_icache_sync_all();
|
||||
|
||||
/*
|
||||
* Pages were allocated during the secondary bootstrap for the
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: cpuswitch.S,v 1.2 2001/04/17 16:14:57 toshii Exp $ */
|
||||
/* $NetBSD: cpuswitch.S,v 1.3 2002/01/25 19:19:29 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1994-1998 Mark Brinicombe.
|
||||
@ -533,7 +533,7 @@ switch_exited:
|
||||
stmfd sp!, {r0-r3}
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lcs_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lcs_cache_purged:
|
||||
ldmfd sp!, {r0-r3}
|
||||
@ -639,7 +639,7 @@ ENTRY(switch_exit)
|
||||
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lse_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lse_cache_purged:
|
||||
ldmfd sp!, {r0-r3}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: locore.S,v 1.4 2001/12/20 01:20:28 thorpej Exp $ */
|
||||
/* $NetBSD: locore.S,v 1.5 2002/01/25 19:19:30 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (C) 1994-1997 Mark Brinicombe
|
||||
@ -108,7 +108,7 @@ ENTRY_NP(cpu_reset)
|
||||
|
||||
ldr r0, Lcpufuncs
|
||||
add lr, pc, #Lboot_cache_purged - . - 8
|
||||
ldr pc, [r0, #CF_CACHE_PURGE_ID]
|
||||
ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
|
||||
|
||||
Lboot_cache_purged:
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: netwinder_machdep.c,v 1.14 2001/11/23 21:18:35 thorpej Exp $ */
|
||||
/* $NetBSD: netwinder_machdep.c,v 1.15 2002/01/25 19:19:30 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997,1998 Mark Brinicombe.
|
||||
@ -728,7 +728,7 @@ initarm(bootinfo)
|
||||
memcpy((char *)0x00000000, page0, page0_end - page0);
|
||||
|
||||
/* We have modified a text page so sync the icache */
|
||||
cpu_cache_syncI();
|
||||
cpu_icache_sync_all();
|
||||
|
||||
/*
|
||||
* Pages were allocated during the secondary bootstrap for the
|
||||
@ -830,38 +830,6 @@ process_kernel_args(args)
|
||||
parse_mi_bootargs(boot_args);
|
||||
}
|
||||
|
||||
#if 0
|
||||
void
|
||||
arm32_cachectl(va, len, flags)
|
||||
vm_offset_t va;
|
||||
int len;
|
||||
int flags;
|
||||
{
|
||||
pt_entry_t *ptep, pte;
|
||||
int loop;
|
||||
vm_offset_t addr;
|
||||
|
||||
/* printf("arm32_cachectl(%x,%x,%x)\n", va, len, flags);*/
|
||||
|
||||
if (flags & 1) {
|
||||
addr = va;
|
||||
loop = len;
|
||||
while (loop > 0) {
|
||||
ptep = vtopte(addr & (~PGOFSET));
|
||||
pte = *ptep;
|
||||
|
||||
*ptep = (pte & ~(PT_C | PT_B)) | (flags & (PT_C | PT_B));
|
||||
|
||||
loop -= NBPG;
|
||||
addr += NBPG;
|
||||
}
|
||||
tlb_flush();
|
||||
}
|
||||
|
||||
cpu_cache_purgeD_rng(va, len);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern struct bus_space footbridge_pci_io_bs_tag;
|
||||
extern struct bus_space footbridge_pci_mem_bs_tag;
|
||||
void footbridge_pci_bs_tag_init __P((void));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user