Add register definitions for the i80200 Interrupt Controller Unit,
Bus Controller Unit, and Performance Monitoring Unit.
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/* $NetBSD: i80200reg.h,v 1.1 2001/12/01 05:46:19 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_XSCALE_I80200REG_H_
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#define _ARM_XSCALE_I80200REG_H_
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/*
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* Register definitions for the Intel 80200 XScale processor.
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*/
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/*
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* Interrupt Controller Unit (CP13)
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*
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* CP13.0 Interrupt Control
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* CP13.1 Interrupt Source
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* CP13.2 Interrupt Steer
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*/
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#define INTCTL_FM (1U << 0) /* external FIQ# enable */
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#define INTCTL_IM (1U << 1) /* external IRQ# enable */
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#define INTCTL_PM (1U << 2) /* PMU interrupt enable */
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#define INTCTL_BM (1U << 3) /* BCU interrupt enable */
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#define INTSRC_PI (1U << 28) /* PMU interrupt */
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#define INTSRC_BM (1U << 29) /* BCU interrupt */
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#define INTSRC_II (1U << 30) /* external IRQ# */
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#define INTSRC_FI (1U << 31) /* external FIQ# */
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#define INTSTR_PS (1U << 0) /* PMU 0 = IRQ, 1 = FIQ */
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#define INTSTR_BS (1U << 1) /* BCU 0 = IRQ, 1 = FIQ */
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/*
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* Bus Controller Unit (CP13)
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*
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* CP13.0.1 BCU Control
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* CP13.1.1 BCUMOD
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* CP13.4.1 ELOG0 (ECC error log)
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* CP13.5.1 ELOG1
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* CP13.6.1 ECAR0 (ECC error address)
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* CP13.7.1 ECAR1
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* CP13.8.1 ECTST (ECC test)
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*/
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#define BCUCTL_SR (1U << 0) /* single bit error report enable */
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#define BCUCTL_SC (1U << 2) /* single bit correct enable */
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#define BCUCTL_EE (1U << 3) /* ECC enable */
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#define BCUCTL_E0 (1U << 28) /* ELOG0 valid */
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#define BCUCTL_E1 (1U << 29) /* ELOG1 valid */
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#define BCUCTL_EV (1U << 30) /* error overflow */
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#define BCUCTL_TP (1U << 31) /* transactions pending */
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#define BCUMOD_AF (1U << 0) /* aligned fetch */
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#define ELOGx_SYN(x) ((x) & 0xff) /* ECC syndrome */
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#define ELOGx_ET(x) (((x) >> 29) & 3)/* error type */
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#define ELOGx_ET_SB 0 /* single-bit */
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#define ELOGx_ET_MB 1 /* multi-bit */
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#define ELOGx_ET_BA 2 /* bus abort */
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#define ELOGx_RW (1U << 31) /* direction 0 = read 1 = write */
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/*
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* Performance Monitoring Unit (CP14)
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*
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* CP14.0 Performance Monitor Control Register
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* CP14.1 Clock Counter
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* CP14.2 Performance Counter Register 0
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* CP14.3 Performance Counter Register 1
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*/
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#define PMNC_E (1U << 0) /* enable counters */
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#define PMNC_P (1U << 1) /* reset both PMNs to 0 */
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#define PMNC_C (1U << 2) /* clock counter reset */
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#define PMNC_D (1U << 3) /* clock counter / 64 */
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#define PMNC_PMN0_IE (1U << 4) /* enable PMN0 interrupt */
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#define PMNC_PMN1_IE (1U << 5) /* enable PMN1 interrupt */
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#define PMNC_CC_IE (1U << 6) /* enable clock counter interrupt */
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#define PMNC_PMN0_IF (1U << 8) /* PMN0 overflow/interrupt */
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#define PMNC_PMN1_IF (1U << 9) /* PMN1 overflow/interrupt */
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#define PMNC_CC_IF (1U << 10) /* clock counter overflow/interrupt */
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#define PMNC_EVCNT0(x) ((x) << 12) /* event to count for PMN0 */
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#define PMNC_EVCNT1(x) ((x) << 20) /* event to count for PMN1 */
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#endif /* _ARM_XSCALE_I80200REG_H_ */
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