Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32.
Shouldn't effect any currently in tree ports.
This commit is contained in:
chris
parent
b5269c31d1
commit
878db7cfb8
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@ -1,6 +1,7 @@
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/* $NetBSD: cpufunc.c,v 1.8 2001/06/03 13:38:14 bjh21 Exp $ */
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/* $NetBSD: cpufunc.c,v 1.9 2001/06/03 18:32:33 chris Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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* arm8 support code Copyright (c) 1997 ARM Limited
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* arm8 support code Copyright (c) 1997 Causality Limited
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* Copyright (c) 1997 Mark Brinicombe.
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@ -269,6 +270,76 @@ struct cpu_functions arm7_cpufuncs = {
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};
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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struct cpu_functions arm7tdmi_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* domain */
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arm7tdmi_setttb, /* setttb */
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cpufunc_faultstatus, /* faultstatus */
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cpufunc_faultaddress, /* faultaddress */
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/* TLB functions */
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arm7tdmi_tlb_flushID, /* tlb_flushID */
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arm7tdmi_tlb_flushID_SE, /* tlb_flushID_SE */
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arm7tdmi_tlb_flushID, /* tlb_flushI */
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arm7tdmi_tlb_flushID_SE, /* tlb_flushI_SE */
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arm7tdmi_tlb_flushID, /* tlb_flushD */
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arm7tdmi_tlb_flushID_SE, /* tlb_flushD_SE */
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/* Cache functions */
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arm7tdmi_cache_flushID, /* cache_flushID */
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(void *)arm7tdmi_cache_flushID, /* cache_flushID_SE */
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arm7tdmi_cache_flushID, /* cache_flushI */
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(void *)arm7tdmi_cache_flushID, /* cache_flushI_SE */
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arm7tdmi_cache_flushID, /* cache_flushD */
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(void *)arm7tdmi_cache_flushID, /* cache_flushD_SE */
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cpufunc_nullop, /* cache_cleanID s*/
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(void *)cpufunc_nullop, /* cache_cleanID_E s*/
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cpufunc_nullop, /* cache_cleanD s*/
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(void *)cpufunc_nullop, /* cache_cleanD_E */
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arm7tdmi_cache_flushID, /* cache_purgeID s*/
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(void *)arm7tdmi_cache_flushID, /* cache_purgeID_E s*/
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arm7tdmi_cache_flushID, /* cache_purgeD s*/
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(void *)arm7tdmi_cache_flushID, /* cache_purgeD_E s*/
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/* Other functions */
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cpufunc_nullop, /* flush_prefetchbuf */
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cpufunc_nullop, /* drain_writebuf */
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cpufunc_nullop, /* flush_brnchtgt_C */
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(void *)cpufunc_nullop, /* flush_brnchtgt_E */
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(void *)cpufunc_nullop, /* sleep */
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/* Soft functions */
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cpufunc_nullop, /* cache_syncI */
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(void *)cpufunc_nullop, /* cache_cleanID_rng */
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(void *)cpufunc_nullop, /* cache_cleanD_rng */
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(void *)arm7tdmi_cache_flushID, /* cache_purgeID_rng */
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(void *)arm7tdmi_cache_flushID, /* cache_purgeD_rng */
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(void *)cpufunc_nullop, /* cache_syncI_rng */
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arm7_dataabt_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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arm7tdmi_context_switch, /* context_switch */
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arm7tdmi_setup /* cpu setup */
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};
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#endif /* CPU_ARM7TDMI */
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#ifdef CPU_ARM8
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struct cpu_functions arm8_cpufuncs = {
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/* CPU functions */
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@ -452,6 +523,15 @@ set_cpufuncs()
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return 0;
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}
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
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CPU_ID_IS7(cputype) &&
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(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
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cpufuncs = arm7tdmi_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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return 0;
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}
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#endif
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#ifdef CPU_ARM8
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if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
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(cputype & 0x0000f000) == 0x00008000) {
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@ -471,7 +551,7 @@ set_cpufuncs()
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/*
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* Bzzzz. And the answer was ...
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*/
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/* panic("No support for this CPU type (%08x) in kernel\n", cputype);*/
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/* panic("No support for this CPU type (%08x) in kernel", cputype);*/
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return(ARCHITECTURE_NOT_PRESENT);
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}
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@ -501,19 +581,19 @@ cpufunc_null_fixup(arg)
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return(ABORT_FIXUP_OK);
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}
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#if defined(CPU_ARM6) || defined(CPU_ARM7)
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#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
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#ifdef DEBUG_FAULT_CORRECTION
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extern int pmap_debug_level;
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#endif
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#endif
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#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \
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defined(CPU_ARM6) || defined(CPU_ARM7)
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defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI)
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/*
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* "Early" data abort fixup.
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*
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* For ARM2, ARM2as, ARM3 and ARM6 (in early-abort mode). Also used
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* indirectly by ARM6 (in late-abort mode) and ARM7.
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* indirectly by ARM6 (in late-abort mode) and ARM7[TDMI].
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*
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* In early aborts, we may have to fix up LDM, STM, LDC and STC.
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*/
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@ -672,7 +752,8 @@ early_abort_fixup(arg)
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}
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#endif /* CPU_ARM2/250/3/6/7 */
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#if (defined(CPU_ARM6) && defined(ARM6_LATE_ABORT)) || defined(CPU_ARM7)
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#if (defined(CPU_ARM6) && defined(ARM6_LATE_ABORT)) || defined(CPU_ARM7) || \
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defined(CPU_ARM7TDMI)
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/*
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* "Late" (base updated) data abort fixup
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*
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@ -863,14 +944,14 @@ late_abort_fixup(arg)
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return early_abort_fixup(arg);
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}
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#endif /* CPU_ARM6(LATE)/7 */
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#endif /* CPU_ARM6(LATE)/7/7TDMI */
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/*
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* CPU Setup code
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*/
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#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM8) || \
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defined(CPU_SA110)
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#if defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
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defined(CPU_ARM8) || defined(CPU_SA110)
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int cpuctrl;
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#define IGN 0
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@ -911,9 +992,10 @@ parse_cpu_options(args, optlist, cpuctrl)
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}
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return(cpuctrl);
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}
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#endif
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#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 || CPU_SA110 */
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#if defined (CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM8)
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#if defined (CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) \
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|| defined(CPU_ARM8)
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struct cpu_option arm678_options[] = {
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#ifdef COMPAT_12
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{ "nocache", IGN, BIC, CPU_CONTROL_IDC_ENABLE },
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@ -926,7 +1008,7 @@ struct cpu_option arm678_options[] = {
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{ NULL, IGN, IGN, 0 }
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};
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#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM8 */
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#endif /* CPU_ARM6 || CPU_ARM7 || CPU_ARM7TDMI || CPU_ARM8 */
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#ifdef CPU_ARM6
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struct cpu_option arm6_options[] = {
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@ -1008,6 +1090,38 @@ arm7_setup(args)
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}
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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struct cpu_option arm7tdmi_options[] = {
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{ "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
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{ "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
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{ "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
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{ "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
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#ifdef COMPAT_12
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{ "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
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#endif /* COMPAT_12 */
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{ "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
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{ NULL, IGN, IGN, 0 }
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};
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void
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arm7tdmi_setup(args)
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char *args;
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{
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cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
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| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
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| CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE;
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cpuctrl = parse_cpu_options(args, arm678_options, cpuctrl);
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cpuctrl = parse_cpu_options(args, arm7tdmi_options, cpuctrl);
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/* Clear out the cache */
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cpu_cache_purgeID();
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/* Set the control register */
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cpu_control(0xffffffff, cpuctrl);
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}
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#endif /* CPU_ARM7TDMI */
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#ifdef CPU_ARM8
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struct cpu_option arm8_options[] = {
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{ "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
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@ -1,6 +1,7 @@
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/* $NetBSD: cpufunc_asm.S,v 1.2 2001/06/02 19:01:03 bjh21 Exp $ */
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/* $NetBSD: cpufunc_asm.S,v 1.3 2001/06/03 18:32:33 chris Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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* arm8 support code Copyright (c) 1997 ARM Limited
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* arm8 support code Copyright (c) 1997 Causality Limited
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* Copyright (c) 1997,1998 Mark Brinicombe.
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@ -186,6 +187,25 @@ ENTRY(arm67_setttb)
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mov pc, lr
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#endif /* CPU_ARM6 || CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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ENTRY(arm7tdmi_setttb)
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mov r1,r0 /* store the ttb in a safe place */
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mov r2,lr /* ditto with lr */
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bl _C_LABEL(arm7tdmi_cache_flushID)
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/* Write the TTB */
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mcr p15, 0, r1, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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bl _C_LABEL(arm7tdmi_tlb_flushID)
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/* For good measure we will flush the IDC as well */
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bl _C_LABEL(arm7tdmi_cache_flushID)
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mov pc, r2
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#endif /* CPU_7TDMI */
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#ifdef CPU_ARM8
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ENTRY(arm8_setttb)
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/* We need to clean and flush the cache as it uses virtual
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@ -274,6 +294,16 @@ ENTRY(arm67_tlb_purge)
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mov pc, lr
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#endif /* CPU_ARM6 || CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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ENTRY(arm7tdmi_tlb_flushID)
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mov r0,#0
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mcr p15, 0, r0, c8, c7, 0
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mov pc,lr
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ENTRY(arm7tdmi_tlb_flushID_SE)
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mcr p15, 0, r0, c8, c7, 1
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mov pc,lr
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#endif
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#ifdef CPU_ARM8
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ENTRY(arm8_tlb_flushID)
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mcr 15, 0, r0, c8, c7, 0 /* flush I+D tlb */
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@ -323,6 +353,18 @@ ENTRY(arm67_cache_flush)
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mov pc, lr
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#endif /* CPU_ARM6 || CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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ENTRY(arm7tdmi_cache_flushID)
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0
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/* Make sure that the pipeline is emptied */
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mov r0, r0
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mov r0, r0
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mov pc,lr
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#endif
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#ifdef CPU_ARM8
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ENTRY(arm8_cache_flushID)
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mcr 15, 0, r0, c7, c7, 0 /* flush I+D cache */
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@ -775,6 +817,10 @@ ENTRY(arm67_context_switch)
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mov pc, lr
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#endif
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#ifdef CPU_ARM7TDMI
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ENTRY(arm7tdmi_context_switch)
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b arm7tdmi_setttb
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#endif
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#ifdef CPU_ARM8
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ENTRY(arm8_context_switch)
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/* Switch the memory to the new process */
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu.c,v 1.2 2001/05/13 13:53:08 bjh21 Exp $ */
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/* $NetBSD: cpu.c,v 1.3 2001/06/03 18:32:34 chris Exp $ */
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/*
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* Copyright (c) 1995 Mark Brinicombe.
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@ -294,7 +294,7 @@ const struct cpu_classtab cpu_classes[] = {
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{ "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */
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{ "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */
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{ "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */
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{ "ARM7TDMI", NULL }, /* CPU_CLASS_ARM7TDMI */
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{ "ARM7TDMI", "CPU_ARM7TDMI" },/* CPU_CLASS_ARM7TDMI */
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{ "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
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{ "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */
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{ "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */
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@ -340,6 +340,7 @@ identify_arm_cpu(dv, cpu_number)
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switch (cpu->cpu_class) {
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case CPU_CLASS_ARM6:
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case CPU_CLASS_ARM7:
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case CPU_CLASS_ARM7TDMI:
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case CPU_CLASS_ARM8:
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if ((cpu->cpu_ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
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strcat(cpu->cpu_model, " IDC disabled");
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@ -390,6 +391,9 @@ identify_arm_cpu(dv, cpu_number)
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#ifdef CPU_ARM7
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case CPU_CLASS_ARM7:
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#endif
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#ifdef CPU_ARM7TDMI
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case CPU_CLASS_ARM7TDMI:
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#endif
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#ifdef CPU_ARM8
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case CPU_CLASS_ARM8:
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#endif
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@ -1,4 +1,4 @@
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# $NetBSD: files.arm,v 1.29 2001/05/29 23:03:20 bjh21 Exp $
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# $NetBSD: files.arm,v 1.30 2001/06/03 18:32:33 chris Exp $
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# temporary define to allow easy moving to ../arch/arm/arm32
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defopt ARM32
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@ -7,8 +7,8 @@ defopt ARM32
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defopt opt_progmode.h PROG26 PROG32
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# CPU types
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defopt opt_cputypes.h CPU_ARM2 CPU_ARM250 CPU_ARM3 : PROG26
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defopt opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7500 CPU_ARM8 CPU_SA110
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CPU_SA1110 : PROG32
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defopt opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM7500 CPU_ARM8
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CPU_SA110 CPU_SA1110 : PROG32
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# Floating point emulator
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defopt ARMFPE
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.h,v 1.4 2001/06/02 21:03:32 bjh21 Exp $ */
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/* $NetBSD: cpufunc.h,v 1.5 2001/06/03 18:32:34 chris Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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@ -207,6 +207,16 @@ void arm6_setup __P((char *string));
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void arm7_setup __P((char *string));
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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int arm7_dataabt_fixup __P((void *arg));
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void arm7tdmi_setup __P((char *string));
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void arm7tdmi_setttb __P((u_int ttb));
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void arm7tdmi_tlb_flushID __P((void));
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void arm7tdmi_tlb_flushID_SE __P((u_int va));
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void arm7tdmi_cache_flushID __P((void));
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void arm7tdmi_context_switch __P((void));
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#endif /* CPU_ARM7TDMI */
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#ifdef CPU_ARM8
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void arm8_setttb __P((u_int ttb));
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void arm8_tlb_flushID __P((void));
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