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Purge CPU_ARM7500. Thanks to Reinoud's work, it's no longer needed.

This commit is contained in:
bjh21 2001-07-10 20:43:57 +00:00
parent 75e45c9dee
commit ea353a48e1
13 changed files with 20 additions and 109 deletions
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4
sys/arch/arm/conf/files.arm
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@ -1,4 +1,4 @@
# $NetBSD: files.arm,v 1.33 2001/07/08 23:20:04 rjs Exp $
# $NetBSD: files.arm,v 1.34 2001/07/10 20:43:57 bjh21 Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defopt ARM32
@ -7,7 +7,7 @@ defopt ARM32
defopt opt_progmode.h PROG26 PROG32
# CPU types
defopt opt_cputypes.h CPU_ARM2 CPU_ARM250 CPU_ARM3 : PROG26
defopt opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM7500 CPU_ARM8
defopt opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
CPU_SA110 CPU_SA1100 CPU_SA1110 : PROG32
# Floating point emulator

8
sys/arch/arm/include/cpu.h
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@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.14 2001/07/09 21:46:19 reinoud Exp $ */
/* $NetBSD: cpu.h,v 1.15 2001/07/10 20:43:57 bjh21 Exp $ */
/*
* Copyright (c) 1994-1996 Mark Brinicombe.
@ -85,12 +85,6 @@
#error "Support for at least one CPU type must be configured into the kernel"
#endif
#ifdef CPU_ARM7500
#ifndef CPU_ARM7
#error "option CPU_ARM7 is required with CPU_ARM7500"
#endif
#endif /* CPU_ARM7500 */
#endif /* !_LKM */

10
sys/arch/arm32/conf/A7000
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@ -1,4 +1,4 @@
# $NetBSD: A7000,v 1.45 2001/07/10 00:52:29 bjh21 Exp $
# $NetBSD: A7000,v 1.46 2001/07/10 20:43:58 bjh21 Exp $
#
# A7000 - Full A7000 configuration
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
#options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

10
sys/arch/arm32/conf/A7INST
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@ -1,4 +1,4 @@
# $NetBSD: A7INST,v 1.34 2001/07/10 00:52:30 bjh21 Exp $
# $NetBSD: A7INST,v 1.35 2001/07/10 20:43:58 bjh21 Exp $
#
# A7INST - A7000 install configuration
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
#options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

10
sys/arch/arm32/conf/GENERIC
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@ -1,11 +1,11 @@
# $NetBSD: GENERIC,v 1.83 2001/07/10 00:52:30 bjh21 Exp $
# $NetBSD: GENERIC,v 1.84 2001/07/10 20:43:58 bjh21 Exp $
#
# GENERIC -- everything that's currently supported
#
include "arch/arm32/conf/std.arm32"
#ident "GENERIC-$Revision: 1.83 $"
#ident "GENERIC-$Revision: 1.84 $"
# estimated number of users
maxusers 32
@ -16,18 +16,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
#options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

10
sys/arch/arm32/conf/NC
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@ -1,4 +1,4 @@
# $NetBSD: NC,v 1.5 2001/07/10 00:52:31 bjh21 Exp $
# $NetBSD: NC,v 1.6 2001/07/10 20:43:58 bjh21 Exp $
#
# NC - with vidcconsole
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
#options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

10
sys/arch/arm32/conf/NC_WSCONS
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@ -1,4 +1,4 @@
# $NetBSD: NC_WSCONS,v 1.6 2001/07/10 00:52:31 bjh21 Exp $
# $NetBSD: NC_WSCONS,v 1.7 2001/07/10 20:43:58 bjh21 Exp $
#
# NC - with wscons
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
#options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

10
sys/arch/arm32/conf/RC7500
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@ -1,4 +1,4 @@
# $NetBSD: RC7500,v 1.35 2001/07/08 16:32:15 abs Exp $
# $NetBSD: RC7500,v 1.36 2001/07/10 20:43:59 bjh21 Exp $
#
# RC7500 - Config for the VLSI RC7500 board
#
@ -18,18 +18,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
#options CPU_SA110 # Support the SA110 core
#options CPU_ARM6 # Support the ARM6 core
#options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options IOMD # We have an IOMD
#options RISCPC # We are a RiscPC

8
sys/arch/arm32/conf/RISCPC
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@ -1,4 +1,4 @@
# $NetBSD: RISCPC,v 1.36 2001/07/10 00:52:31 bjh21 Exp $
# $NetBSD: RISCPC,v 1.37 2001/07/10 20:43:59 bjh21 Exp $
#
# RISCPC -- Full RiscPC config
#
@ -15,8 +15,6 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
@ -26,10 +24,6 @@ options CPU_ARM7 # Support the ARM7 core
# For StrongARM only kernels
#makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"
# For A7000, Stork and other ARM7500 machines
#options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

8
sys/arch/arm32/conf/RPCINST
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@ -1,4 +1,4 @@
# $NetBSD: RPCINST,v 1.33 2001/07/10 00:52:32 bjh21 Exp $
# $NetBSD: RPCINST,v 1.34 2001/07/10 20:43:59 bjh21 Exp $
#
# RPCINST -- RiscPC install configuration
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
#options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

8
sys/arch/arm32/conf/RPC_WSCONS
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@ -1,4 +1,4 @@
# $NetBSD: RPC_WSCONS,v 1.7 2001/07/10 00:52:32 bjh21 Exp $
# $NetBSD: RPC_WSCONS,v 1.8 2001/07/10 20:43:59 bjh21 Exp $
#
# RPC_WSCONS -- Full RiscPC config with wscons
#
@ -15,8 +15,6 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
@ -26,10 +24,6 @@ options CPU_ARM7 # Support the ARM7 core
# For StrongARM only kernels
#makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"
# For A7000, Stork and other ARM7500 machines
#options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

8
sys/arch/arm32/conf/VOYAGER
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@ -1,4 +1,4 @@
# $NetBSD: VOYAGER,v 1.55 2001/07/10 00:52:33 bjh21 Exp $
# $NetBSD: VOYAGER,v 1.56 2001/07/10 20:43:59 bjh21 Exp $
#
# VOYAGER - Mark's development kernel
#
@ -15,18 +15,12 @@ options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
#options NTP # NTP phase/frequency locked loop
# CPU options
# For standard RiscPC's
options CPU_SA110 # Support the SA110 core
options CPU_ARM6 # Support the ARM6 core
options CPU_ARM7 # Support the ARM7 core
options CPU_ARM8 # Support the ARM8 core
#options ARM6_LATE_ABORT # ARM6XX late abort support
# For A7000, Stork and other ARM7500 machines
#options CPU_ARM7 # Support the ARM7 core
#options CPU_ARM7500 # We are actually an ARM7500
# Architecture options
options RISCPC # We are a RiscPC
#options RC7500 # We are a RC7500

25
sys/arch/arm32/riscpc/rpc_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: rpc_machdep.c,v 1.49 2001/07/09 21:46:20 reinoud Exp $ */
/* $NetBSD: rpc_machdep.c,v 1.50 2001/07/10 20:44:00 bjh21 Exp $ */
/*
* Copyright (c) 2000-2001 Reinoud Zandijk.
@ -445,7 +445,6 @@ initarm_new_bootloader(bootconf)
u_int l2pagetable;
extern char page0[], page0_end[];
struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;
int id;
pv_addr_t kernel_l1pt;
pv_addr_t kernel_ptpt;
@ -522,17 +521,6 @@ initarm_new_bootloader(bootconf)
/** START OF REAL NEW STUFF */
/* Check if we are having the right kernel */
id = ReadByte(IOMD_HW_BASE + (IOMD_ID0 << 2))
| (ReadByte(IOMD_HW_BASE + (IOMD_ID1 << 2)) << 8);
switch (id) {
case ARM7500_IOC_ID:
#ifndef CPU_ARM7500
panic2(("Encountered ARM7500 IOMD but no ARM7500 kernel support"));
#endif /* CPU_ARM7500 */
break;
}
/* Check to make sure the page size is correct */
if (NBPG != bootconfig.pagesize)
panic2(("Page size is %d bytes in stead of %d !! (huh?)\n", bootconfig.pagesize, NBPG));
@ -1126,7 +1114,6 @@ initarm_old_bootloader(bootconf)
u_int l2pagetable;
extern char page0[], page0_end[];
struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;
int id;
pv_addr_t kernel_l1pt;
pv_addr_t kernel_ptpt;
@ -1404,16 +1391,6 @@ initarm_old_bootloader(bootconf)
if (bootconfig.vram[0].pages != 0)
printf("done.\n");
id = ReadByte(IOMD_BASE + (IOMD_ID0 << 2))
| (ReadByte(IOMD_BASE + (IOMD_ID1 << 2)) << 8);
switch (id) {
case ARM7500_IOC_ID:
#ifndef CPU_ARM7500
panic("Encountered ARM7500 IOMD but no ARM7500 kernel support");
#endif /* CPU_ARM7500 */
break;
}
/*
* Ok we have finished the primary boot strap. All this has done is to
* allow us to access all the physical memory from known virtual