Commit Graph

70 Commits

Author SHA1 Message Date
Stanislav Shwartsman
852b5c3749 implemented SHA new instructions announced in recent Intel SDM extensions document rev015 2013-07-24 18:44:22 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm)
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
5d66e8450e implemented ADCX/ADOX instructions from rev013 of arch extensions published by Intel 2012-07-12 14:51:54 +00:00
Stanislav Shwartsman
bb7a648d91 Major commit !
------------

Implemented SVN nested paging support - the Virtual Box boots perfectly with Nested Paging guest !
A lot of code duplication was added for now - major cleanup will follow later.

! Added AMD Phenom X3 8650 (Toliman) configuration to the CPUDB - this configuration has Nested Paging enabled.

Some CPUID modules rework done to enable Toliman configuration.

Ckean up 'executable' attribute from all CPU source files.
2012-02-13 23:29:01 +00:00
Stanislav Shwartsman
abda3a967c added two AMD CPUs to CPUDB 2011-12-29 14:23:22 +00:00
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet)
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
42a0a178eb disasm for XOP instructions 2011-10-30 08:58:49 +00:00
Stanislav Shwartsman
aad57310c2 disasm for FMA4, better dbg print SSE rounding control with MXCSR 2011-10-06 20:33:10 +00:00
Stanislav Shwartsman
e3dae7adb1 added disasm for avx fma instructions 2011-09-29 19:50:27 +00:00
Stanislav Shwartsman
50207eeb90 - Added support for AMD SSE4A emulation, the instructions can be enabled
using .bochsrc CPUID option.
2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
3f230d115e clean disasm opcodes.inc 2011-09-13 20:43:15 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
1dc8f56f06 disasm for AVX2 gather 2011-08-28 21:38:53 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87 MOVBE instruction exists only in memory form 2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
e796e6a96c disasm avx2 new instructions (no gather yet) 2011-08-24 20:55:23 +00:00
Stanislav Shwartsman
35ec48d17d small fixes 2011-08-13 18:39:17 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
5ea65d1753 fix for disasm 2011-08-10 22:11:12 +00:00
Stanislav Shwartsman
3f075d1ddf disasm for invpcid 2011-06-10 12:49:52 +00:00
Stanislav Shwartsman
04e9254e2c AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A 2011-05-30 20:15:50 +00:00
Volker Ruppert
c78026a9a2 - deleted executable properties from source files 2011-04-03 10:29:19 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX
(and for AVX)
2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support
many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
00981cd7a6 Adding Id and Rev property to all files 2011-02-24 22:05:47 +00:00
Stanislav Shwartsman
dc72673bb3 Fixed arpl disasm 2010-10-11 15:33:11 +00:00
Stanislav Shwartsman
7f7c249934 disasm and some cpuid code according to recently published AVX_319433-007.pdf document 2010-07-22 15:12:08 +00:00
Stanislav Shwartsman
2dbe559ad9 simpler disasm tables 2010-05-23 20:05:14 +00:00
Stanislav Shwartsman
69517f9143 Fix PEXTRB/PEXTRW/PEXTRD/EXTRACTPS 2010-04-02 19:01:17 +00:00
Stanislav Shwartsman
2efb11f2bc fixes 2010-03-30 18:12:19 +00:00
Stanislav Shwartsman
cceb0a5a17 invept/invvpid disasm 2010-03-26 10:39:40 +00:00
Stanislav Shwartsman
9147ac4b63 MOVMSKPD/PS fix 2010-03-19 14:43:13 +00:00
Stanislav Shwartsman
c4412bf357 movdq2q fix 2010-03-19 10:44:02 +00:00
Stanislav Shwartsman
70dc124b3a 1st step of moving CPU options to runtime 2010-02-24 19:27:51 +00:00
Stanislav Shwartsman
08aa9fef6d disasm updates 2010-02-09 20:28:12 +00:00
Stanislav Shwartsman
eae084920a optimized decode tables 2010-01-31 09:45:27 +00:00
Stanislav Shwartsman
b5d1677848 GETSC instruction disasm 2010-01-11 21:27:59 +00:00
Stanislav Shwartsman
880ee7f872 sort opcodes.inc 2009-12-17 09:17:45 +00:00
Stanislav Shwartsman
db8ecc535e added mclmulqdq disasm 2009-12-17 09:13:35 +00:00
Stanislav Shwartsman
7254ea36a1 copyright fixes + small optimization 2009-10-14 20:45:29 +00:00
Stanislav Shwartsman
8a4ac11700 more verbose maskmov disasm 2009-08-21 13:45:38 +00:00
Stanislav Shwartsman
db098a1205 Fix dependencies of CPU code from disasm library
Regent Makefile.in for CPU
2009-01-19 19:01:03 +00:00
Stanislav Shwartsman
c09e2b6418 Fixes in disasm 2008-10-01 09:10:54 +00:00
Stanislav Shwartsman
87103c2437 Support for disasm of MOVBE Intel Atom(R) instruction 2008-08-11 17:55:57 +00:00
Stanislav Shwartsman
a85dfc7617 Added disasm for AES instructions 2008-05-25 15:42:26 +00:00
Stanislav Shwartsman
1a34834db9 Fixed disasm for SSE4.2 instr 2008-04-18 14:09:24 +00:00