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disasm avx2 new instructions (no gather yet)

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This commit is contained in:
Stanislav Shwartsman 2011-08-24 20:55:23 +00:00
parent a1b9a8e190
commit e796e6a96c
6 changed files with 114 additions and 47 deletions
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9
bochs/disasm/dis_decode.cc
View File

@ -289,6 +289,10 @@ x86_insn disassembler::decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_
entry = &(OPCODE_TABLE(entry)[insn.os_64 ? 2 : insn.os_32]);
break;
case _GRPVEXW:
entry = &(OPCODE_TABLE(entry)[insn.vex_w]);
break;
default:
printf("Internal disassembler error - unknown attribute !\n");
return x86_insn(is_32, is_64);
@ -391,11 +395,12 @@ unsigned disassembler::decode_vex(x86_insn *insn)
if (b2 & 0x80) {
insn->os_64 = 1;
insn->os_32 = 1;
insn->vex_w = 1;
}
}
insn->vex_override = 15 - ((b2 >> 3) & 0xf);
insn->vex_vl = (b2 >> 2) & 0x1;
insn->vex_vvv = 15 - ((b2 >> 3) & 0xf);
insn->vex_l = (b2 >> 2) & 0x1;
insn->b1 = fetch_byte() + 256 * vex_opcode_extension;
return b2 & 0x3;
}

25
bochs/disasm/dis_groups.cc
View File

@ -405,7 +405,7 @@ void disassembler::Qq(const x86_insn *insn)
// xmm/ymm register
void disassembler::Udq(const x86_insn *insn)
{
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->rm);
dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->rm);
}
void disassembler::Ups(const x86_insn *insn) { Udq(insn); }
@ -413,7 +413,7 @@ void disassembler::Upd(const x86_insn *insn) { Udq(insn); }
void disassembler::Vq(const x86_insn *insn)
{
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->nnn);
dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->nnn);
}
void disassembler::Vdq(const x86_insn *insn) { Vq(insn); }
@ -426,17 +426,24 @@ void disassembler::VIb(const x86_insn *insn)
{
unsigned vreg = fetch_byte() >> 4;
if (! insn->is_64) vreg &= 7;
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], vreg);
dis_sprintf("%s%d", vector_reg_name[insn->vex_l], vreg);
}
void disassembler::Hdq(const x86_insn *insn)
{
dis_sprintf("%s%d", vector_reg_name[insn->vex_vl], insn->vex_override);
dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->vex_vvv);
}
void disassembler::Hps(const x86_insn *insn) { Hdq(insn); }
void disassembler::Hpd(const x86_insn *insn) { Hdq(insn); }
void disassembler::Wb(const x86_insn *insn)
{
if (insn->mod == 3) Udq(insn);
else
(this->*resolve_modrm)(insn, B_SIZE);
}
void disassembler::Ww(const x86_insn *insn)
{
if (insn->mod == 3) Udq(insn);
@ -462,7 +469,7 @@ void disassembler::Wdq(const x86_insn *insn)
{
if (insn->mod == 3) Udq(insn);
else
(this->*resolve_modrm)(insn, XMM_SIZE + insn->vex_vl);
(this->*resolve_modrm)(insn, XMM_SIZE + insn->vex_l);
}
void disassembler::Wsd(const x86_insn *insn) { Wq(insn); }
@ -521,9 +528,9 @@ void disassembler::Md(const x86_insn *insn) { OP_M(insn, D_SIZE); }
void disassembler::Mq(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
void disassembler::Mt(const x86_insn *insn) { OP_M(insn, T_SIZE); }
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
void disassembler::Mss(const x86_insn *insn) { OP_M(insn, D_SIZE); }
void disassembler::Msd(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
@ -615,7 +622,7 @@ void disassembler::OP_sY(const x86_insn *insn, unsigned size)
}
void disassembler::sYq(const x86_insn *insn) { OP_sY(insn, Q_SIZE); }
void disassembler::sYdq(const x86_insn *insn) { OP_sY(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::sYdq(const x86_insn *insn) { OP_sY(insn, XMM_SIZE + insn->vex_l); }
#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))

3
bochs/disasm/dis_tables.h
View File

@ -34,6 +34,7 @@
#define _GRPRM 9
#define _GRP3BOP 10
#define _GRP64B 11
#define _GRPVEXW 12
/* ************************************************************************ */
#define GRPSSE(n) _GRPSSE, BxDisasmGroupSSE_##n
@ -45,6 +46,7 @@
#define GRP3DNOW _GRP3DNOW, BxDisasm3DNowGroup
#define GR3BTAB(n) _GRP3BOP, BxDisasm3ByteOpTable##n
#define GR64BIT(n) _GRP64B, BxDisasmGrpOs64B_##n
#define GRPVEXW(n) _GRPVEXW, BxDisasmGrpVexW_##n
/* ************************************************************************ */
/* ************************************************************************ */
@ -139,6 +141,7 @@
#define Upd &disassembler::Upd
#define Udq &disassembler::Udq
#define Wb &disassembler::Wb
#define Ww &disassembler::Ww
#define Wd &disassembler::Wd
#define Wq &disassembler::Wq

88
bochs/disasm/dis_tables_avx.inc
View File

@ -407,16 +407,44 @@ static BxDisasmOpcodeTable_t BxDisasmGroupModAVXG15[2] = {
/* M */ { GRPN(AVXG15M) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpOs64B_AVX0f3a16[3] = {
/* 16 */ { GRPSSE66(Ia_vpextrd_Ed_Vdq_Ib) },
/* 32 */ { GRPSSE66(Ia_vpextrd_Ed_Vdq_Ib) },
/* 64 */ { GRPSSE66(Ia_vpextrq_Eq_Vdq_Ib) }
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3a16[2] = {
/* 0 */ { GRPSSE66(Ia_vpextrd_Ed_Vdq_Ib) },
/* 1 */ { GRPSSE66(Ia_vpextrq_Eq_Vdq_Ib) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpOs64B_AVX0f3a22[3] = {
/* 16 */ { GRPSSE66(Ia_vpinsrd_Vdq_Hdq_Ed_Ib) },
/* 32 */ { GRPSSE66(Ia_vpinsrd_Vdq_Hdq_Ed_Ib) },
/* 64 */ { GRPSSE66(Ia_vpinsrq_Vdq_Hdq_Eq_Ib) }
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3a22[2] = {
/* 0 */ { GRPSSE66(Ia_vpinsrd_Vdq_Hdq_Ed_Ib) },
/* 1 */ { GRPSSE66(Ia_vpinsrq_Vdq_Hdq_Eq_Ib) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3a00[2] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { GRPSSE66(Ia_vpermq_Vdq_Wdq_Ib) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3a01[2] = {
/* 0 */ { 0, &Ia_Invalid },
/* 1 */ { GRPSSE66(Ia_vpermpd_Vpd_Wpd_Ib) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3845[2] = {
/* 0 */ { GRPSSE66(Ia_vpsrlvd_Vdq_Hdq_Wdq) },
/* 1 */ { GRPSSE66(Ia_vpsrlvq_Vdq_Hdq_Wdq) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f3847[2] = {
/* 0 */ { GRPSSE66(Ia_vpsllvd_Vdq_Hdq_Wdq) },
/* 1 */ { GRPSSE66(Ia_vpsllvq_Vdq_Hdq_Wdq) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f388c[2] = {
/* 0 */ { GRPSSE66(Ia_vmaskmovd_Vdq_Hdq_Mdq) },
/* 1 */ { GRPSSE66(Ia_vmaskmovq_Vdq_Hdq_Mdq) }
};
static BxDisasmOpcodeTable_t BxDisasmGrpVexW_0f388e[2] = {
/* 0 */ { GRPSSE66(Ia_vmaskmovq_Mdq_Hdq_Vdq) },
/* 1 */ { GRPSSE66(Ia_vmaskmovq_Mdq_Hdq_Vdq) }
};
static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
@ -701,10 +729,10 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 13 */ { GRPSSE66(Ia_vcvtph2ps_Vps_Wq) },
/* 14 */ { 0, &Ia_Invalid },
/* 15 */ { 0, &Ia_Invalid },
/* 16 */ { 0, &Ia_Invalid },
/* 16 */ { GRPSSE66(Ia_vpermps_Vps_Hps_Wps) },
/* 17 */ { GRPSSE66(Ia_vptest_Vdq_Wdq) },
/* 18 */ { GRPSSE66(Ia_vbroadcastss_Vps_Mss) },
/* 19 */ { GRPSSE66(Ia_vbroadcastsd_Vpd_Msd) },
/* 18 */ { GRPSSE66(Ia_vbroadcastss_Vps_Wss) },
/* 19 */ { GRPSSE66(Ia_vbroadcastsd_Vpd_Wsd) },
/* 1A */ { GRPSSE66(Ia_vbroadcastf128_Vdq_Mdq) },
/* 1B */ { 0, &Ia_Invalid },
/* 1C */ { GRPSSE66(Ia_vpabsb_Vdq_Hdq_Wdq) },
@ -733,7 +761,7 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 33 */ { GRPSSE66(Ia_vpmovzxwd_Vdq_Wq) },
/* 34 */ { GRPSSE66(Ia_vpmovzxwq_Vdq_Wd) },
/* 35 */ { GRPSSE66(Ia_vpmovzxdq_Vdq_Wq) },
/* 36 */ { 0, &Ia_Invalid },
/* 36 */ { GRPSSE66(Ia_vpermd_Vdq_Hdq_Wdq) },
/* 37 */ { GRPSSE66(Ia_vpcmpgtq_Vdq_Hdq_Wdq) },
/* 38 */ { GRPSSE66(Ia_vpminsb_Vdq_Hdq_Wdq) },
/* 39 */ { GRPSSE66(Ia_vpminsd_Vdq_Hdq_Wdq) },
@ -748,9 +776,9 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 42 */ { 0, &Ia_Invalid },
/* 43 */ { 0, &Ia_Invalid },
/* 44 */ { 0, &Ia_Invalid },
/* 45 */ { 0, &Ia_Invalid },
/* 46 */ { 0, &Ia_Invalid },
/* 47 */ { 0, &Ia_Invalid },
/* 45 */ { GRPVEXW(0f3845) },
/* 46 */ { GRPSSE66(Ia_vpsravd_Vdq_Hdq_Wdq) },
/* 47 */ { GRPVEXW(0f3847) },
/* 48 */ { 0, &Ia_Invalid },
/* 49 */ { 0, &Ia_Invalid },
/* 4A */ { 0, &Ia_Invalid },
@ -767,9 +795,9 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 55 */ { 0, &Ia_Invalid },
/* 56 */ { 0, &Ia_Invalid },
/* 57 */ { 0, &Ia_Invalid },
/* 58 */ { 0, &Ia_Invalid },
/* 59 */ { 0, &Ia_Invalid },
/* 5A */ { 0, &Ia_Invalid },
/* 58 */ { GRPSSE66(Ia_vpbroadcastd_Vdq_Wd) },
/* 59 */ { GRPSSE66(Ia_vpbroadcastq_Vdq_Wq) },
/* 5A */ { GRPSSE66(Ia_vbroadcasti128_Vdq_Mdq) },
/* 5B */ { 0, &Ia_Invalid },
/* 5C */ { 0, &Ia_Invalid },
/* 5D */ { 0, &Ia_Invalid },
@ -799,8 +827,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 75 */ { 0, &Ia_Invalid },
/* 76 */ { 0, &Ia_Invalid },
/* 77 */ { 0, &Ia_Invalid },
/* 78 */ { 0, &Ia_Invalid },
/* 79 */ { 0, &Ia_Invalid },
/* 78 */ { GRPSSE66(Ia_vpbroadcastb_Vdq_Wb) },
/* 79 */ { GRPSSE66(Ia_vpbroadcastw_Vdq_Ww) },
/* 7A */ { 0, &Ia_Invalid },
/* 7B */ { 0, &Ia_Invalid },
/* 7C */ { 0, &Ia_Invalid },
@ -819,9 +847,9 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 89 */ { 0, &Ia_Invalid },
/* 8A */ { 0, &Ia_Invalid },
/* 8B */ { 0, &Ia_Invalid },
/* 8C */ { 0, &Ia_Invalid },
/* 8C */ { GRPVEXW(0f388c) },
/* 8D */ { 0, &Ia_Invalid },
/* 8E */ { 0, &Ia_Invalid },
/* 8E */ { GRPVEXW(0f388e) },
/* 8F */ { 0, &Ia_Invalid },
/* 90 */ { 0, &Ia_Invalid },
/* 91 */ { 0, &Ia_Invalid },
@ -937,9 +965,9 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* FF */ { 0, &Ia_Invalid },
// 256 entries for VEX-encoded 0x0F 0x3A opcodes
/* 00 */ { 0, &Ia_Invalid },
/* 01 */ { 0, &Ia_Invalid },
/* 02 */ { 0, &Ia_Invalid },
/* 00 */ { GRPVEXW(0f3a00) },
/* 01 */ { GRPVEXW(0f3a01) },
/* 02 */ { GRPSSE66(Ia_vpblendd_Vdq_Hdq_Wdq_Ib) },
/* 03 */ { 0, &Ia_Invalid },
/* 04 */ { GRPSSE66(Ia_vpermilps_Vps_Wps_Ib) },
/* 05 */ { GRPSSE66(Ia_vpermilpd_Vpd_Wpd_Ib) },
@ -959,7 +987,7 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 13 */ { 0, &Ia_Invalid },
/* 14 */ { GRPSSE66(Ia_vpextrb_Ebd_Vdq_Ib) },
/* 15 */ { GRPSSE66(Ia_vpextrw_Ewd_Vdq_Ib) },
/* 16 */ { GR64BIT(AVX0f3a16) },
/* 16 */ { GRPVEXW(0f3a16) },
/* 17 */ { GRPSSE66(Ia_vextractps_Ed_Vdq_Ib) },
/* 18 */ { GRPSSE66(Ia_vinsertf128_Vdq_Hdq_Wdq_Ib) },
/* 19 */ { GRPSSE66(Ia_vextractf128_Wdq_Vdq_Ib) },
@ -971,7 +999,7 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 1F */ { 0, &Ia_Invalid },
/* 20 */ { GRPSSE66(Ia_vpinsrb_Vdq_Hdq_Ed_Ib) },
/* 21 */ { GRPSSE66(Ia_vinsertps_Vps_Hps_Wss_Ib) },
/* 22 */ { GR64BIT(AVX0f3a22) },
/* 22 */ { GRPVEXW(0f3a22) },
/* 23 */ { 0, &Ia_Invalid },
/* 24 */ { 0, &Ia_Invalid },
/* 25 */ { 0, &Ia_Invalid },
@ -993,8 +1021,8 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 35 */ { 0, &Ia_Invalid },
/* 36 */ { 0, &Ia_Invalid },
/* 37 */ { 0, &Ia_Invalid },
/* 38 */ { 0, &Ia_Invalid },
/* 39 */ { 0, &Ia_Invalid },
/* 38 */ { GRPSSE66(Ia_vinserti128_Vdq_Hdq_Wdq_Ib) },
/* 39 */ { GRPSSE66(Ia_vextracti128_Wdq_Vdq_Ib) },
/* 3A */ { 0, &Ia_Invalid },
/* 3B */ { 0, &Ia_Invalid },
/* 3C */ { 0, &Ia_Invalid },
@ -1007,7 +1035,7 @@ static BxDisasmOpcodeTable_t BxDisasmOpcodesAVX[256*3] = {
/* 43 */ { 0, &Ia_Invalid },
/* 44 */ { GRPSSE66(Ia_vpclmulqdq_Vdq_Hdq_Wdq_Ib) },
/* 45 */ { 0, &Ia_Invalid },
/* 46 */ { 0, &Ia_Invalid },
/* 46 */ { GRPSSE66(Ia_vperm2i128_Vdq_Hdq_Wdq_Ib) },
/* 47 */ { 0, &Ia_Invalid },
/* 48 */ { 0, &Ia_Invalid },
/* 49 */ { 0, &Ia_Invalid },

8
bochs/disasm/disasm.h
View File

@ -156,7 +156,7 @@ public:
#define BX_AVX_VL128 0
#define BX_AVX_VL256 1
Bit8u vex_override, vex_vl;
Bit8u vex_vvv, vex_l, vex_w;
int is_vex; // 0 - no VEX used, 1 - VEX is used, 2 - invalid VEX
Bit8u modrm, mod, nnn, rm;
Bit8u sib, scale, index, base;
@ -191,8 +191,9 @@ BX_CPP_INLINE x86_insn::x86_insn(bx_bool is32, bx_bool is64)
b1 = 0;
is_vex = 0;
vex_override = 0;
vex_vl = BX_AVX_VL128;
vex_vvv = 0;
vex_l = BX_AVX_VL128;
vex_w = 0;
modrm = mod = nnn = rm = 0;
sib = scale = index = base = 0;
displacement.displ32 = 0;
@ -518,6 +519,7 @@ public:
void VIb(const x86_insn *insn);
// xmm/ymm register or memory operand
void Wb(const x86_insn *insn);
void Ww(const x86_insn *insn);
void Wd(const x86_insn *insn);
void Wq(const x86_insn *insn);

28
bochs/disasm/opcodes.inc
View File

@ -936,12 +936,12 @@ Ia_popw_RX = { "pop", "popw", RX, XX, XX, XX, 0 },
Ia_popw_SS = { "pop", "popw", SS, XX, XX, XX, 0 },
Ia_por_Pq_Qq = { "por", "por", Pq, Qq, XX, XX, IA_MMX },
Ia_por_Vdq_Wdq = { "por", "por", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_prefetchw = { "prefetchw", "prefetchw", Mb, XX, XX, XX, 0 },
Ia_prefetch_hint = { "prefetch_hint", "prefetch_hint", Mb, XX, XX, XX, IA_SSE },
Ia_prefetchnta = { "prefetchnta", "prefetchnta", Mb, XX, XX, XX, IA_SSE },
Ia_prefetcht0 = { "prefetcht0", "prefetcht0", Mb, XX, XX, XX, IA_SSE },
Ia_prefetcht1 = { "prefetcht1", "prefetcht1", Mb, XX, XX, XX, IA_SSE },
Ia_prefetcht2 = { "prefetcht2", "prefetcht2", Mb, XX, XX, XX, IA_SSE },
Ia_prefetchw = { "prefetchw", "prefetchw", Mb, XX, XX, XX, 0 },
Ia_prefix_asize = { "asize", "asize", XX, XX, XX, XX, 0 },
Ia_prefix_cs = { "cs", "cs", XX, XX, XX, XX, 0 },
Ia_prefix_ds = { "ds", "ds", XX, XX, XX, XX, 0 },
@ -1310,8 +1310,9 @@ Ia_vblendps_Vps_Hps_Wps_Ib = { "vblendps", "vblendps", Vps, Hps, Wps, Ib, IA_AVX
Ia_vblendvpd_Vpd_Hpd_Wpd_Ib = { "vblendvpd", "vblendvpd", Vpd, Hpd, Wpd, VIb, IA_AVX },
Ia_vblendvps_Vps_Hps_Wps_Ib = { "vblendvps", "vblendvps", Vps, Hps, Wps, VIb, IA_AVX },
Ia_vbroadcastf128_Vdq_Mdq = { "vbroadcastf128", "vbroadcastf128", Vdq, Mdq, XX, XX, IA_AVX },
Ia_vbroadcastsd_Vpd_Msd = { "vbroadcastsd", "vbroadcastsd", Vpd, Msd, XX, XX, IA_AVX },
Ia_vbroadcastss_Vps_Mss = { "vbroadcastss", "vbroadcastss", Vps, Mss, XX, XX, IA_AVX },
Ia_vbroadcasti128_Vdq_Mdq = { "vbroadcasti128", "vbroadcasti128", Vdq, Mdq, XX, XX, IA_AVX2 },
Ia_vbroadcastsd_Vpd_Wsd = { "vbroadcastsd", "vbroadcastsd", Vpd, Wsd, XX, XX, IA_AVX },
Ia_vbroadcastss_Vps_Wss = { "vbroadcastss", "vbroadcastss", Vps, Wss, XX, XX, IA_AVX },
Ia_vcmppd_Vpd_Hpd_Wpd_Ib = { "vcmppd", "vcmppd", Vpd, Hpd, Wpd, Ib, IA_AVX },
Ia_vcmpps_Vps_Hps_Wps_Ib = { "vcmpps", "vcmpps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_vcmpsd_Vsd_Hpd_Wsd_Ib = { "vcmpsd", "vcmpsd", Vsd, Hpd, Wsd, Ib, IA_AVX },
@ -1345,20 +1346,26 @@ Ia_vdpps_Vps_Hps_Wps_Ib = { "vdpps", "vdpps", Vps, Hps, Wps, Ib, IA_AVX },
Ia_verr = { "verr", "verr", Ew, XX, XX, XX, 0 },
Ia_verw = { "verw", "verw", Ew, XX, XX, XX, 0 },
Ia_vextractf128_Wdq_Vdq_Ib = { "vextractf128", "vextractf128", Wdq, Vdq, Ib, XX, IA_AVX },
Ia_vextracti128_Wdq_Vdq_Ib = { "vextracti128", "vextracti128", Wdq, Vdq, Ib, XX, IA_AVX2 },
Ia_vextractps_Ed_Vdq_Ib = { "vextractps", "vextractps", Ed, Vdq, Ib, XX, IA_AVX },
Ia_vhaddpd_Vpd_Hpd_Wpd = { "vhaddpd", "vhaddpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vhaddps_Vps_Hps_Wps = { "vhaddps", "vhaddps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vhsubpd_Vpd_Hpd_Wpd = { "vhsubpd", "vhsubpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vhsubps_Vps_Hps_Wps = { "vhsubps", "vhsubps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vinsertf128_Vdq_Hdq_Wdq_Ib = { "vinsertf128", "vinsertf128", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vinserti128_Vdq_Hdq_Wdq_Ib = { "vinserti128", "vinserti128", Vdq, Hdq, Wdq, Ib, IA_AVX2 },
Ia_vinsertps_Vps_Hps_Wss_Ib = { "vinsertps", "vinsertps", Vps, Hps, Wss, Ib, IA_AVX },
Ia_vlddqu_Vdq_Mdq = { "vlddqu", "vlddqu", Vdq, Mdq, XX, XX, IA_AVX },
Ia_vldmxcsr = { "vldmxcsr", "vldmxcsr", Md, XX, XX, XX, IA_AVX },
Ia_vmaskmovd_Mdq_Hdq_Vdq = { "vmaskmovd", "vmaskmovd", Mdq, Hdq, Vdq, XX, IA_AVX2 },
Ia_vmaskmovd_Vdq_Hdq_Mdq = { "vmaskmovd", "vmaskmovd", Vdq, Hdq, Mdq, XX, IA_AVX2 },
Ia_vmaskmovdqu_Vdq_Udq = { "vmaskmovdqu", "vmaskmovdqu", Vdq, Udq, XX, XX, IA_AVX },
Ia_vmaskmovpd_Mpd_Hpd_Vpd = { "vmaskmovpd", "vmaskmovpd", Mpd, Hpd, Vpd, XX, IA_AVX },
Ia_vmaskmovpd_Vpd_Hpd_Mpd = { "vmaskmovpd", "vmaskmovpd", Vpd, Hpd, Mpd, XX, IA_AVX },
Ia_vmaskmovps_Mps_Hps_Vps = { "vmaskmovps", "vmaskmovps", Mps, Hps, Vps, XX, IA_AVX },
Ia_vmaskmovps_Vps_Hps_Mps = { "vmaskmovps", "vmaskmovps", Vps, Hps, Mps, XX, IA_AVX },
Ia_vmaskmovq_Mdq_Hdq_Vdq = { "vmaskmovq", "vmaskmovq", Mdq, Hdq, Vdq, XX, IA_AVX2 },
Ia_vmaskmovq_Vdq_Hdq_Mdq = { "vmaskmovq", "vmaskmovq", Vdq, Hdq, Mdq, XX, IA_AVX2 },
Ia_vmaxpd_Vpd_Hpd_Wpd = { "vmaxpd", "vmaxpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vmaxps_Vps_Hps_Wps = { "vmaxps", "vmaxps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vmaxsd_Vsd_Hpd_Wsd = { "vmaxsd", "vmaxsd", Vsd, Hpd, Wsd, XX, IA_AVX },
@ -1449,8 +1456,13 @@ Ia_vpand_Vdq_Hdq_Wdq = { "vpand", "vpand", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpandn_Vdq_Hdq_Wdq = { "vpandn", "vpandn", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpavgb_Vdq_Hdq_Wdq = { "vpavgb", "vpavgb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpavgw_Vdq_Hdq_Wdq = { "vpavgw", "vpavgw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpblendd_Vdq_Hdq_Wdq_Ib = { "vpblendd", "vpblendd", Vdq, Hdq, Wdq, Ib, IA_AVX2 },
Ia_vpblendvb_Vdq_Hdq_Wdq_Ib = { "vpblendvb", "vpblendvb", Vdq, Hdq, Wdq, VIb, IA_AVX },
Ia_vpblendw_Vdq_Hdq_Wdq_Ib = { "vpblendw", "vpblendw", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpbroadcastb_Vdq_Wb = { "vpbroadcastb", "vpbroadcastb", Vdq, Wb, XX, XX, IA_AVX2 },
Ia_vpbroadcastd_Vdq_Wd = { "vpbroadcastd", "vpbroadcastd", Vdq, Wd, XX, XX, IA_AVX2 },
Ia_vpbroadcastq_Vdq_Wq = { "vpbroadcastq", "vpbroadcastq", Vdq, Wq, XX, XX, IA_AVX2 },
Ia_vpbroadcastw_Vdq_Ww = { "vpbroadcastw", "vpbroadcastw", Vdq, Ww, XX, XX, IA_AVX2 },
Ia_vpclmulqdq_Vdq_Hdq_Wdq_Ib = { "vpclmulqdq", "vpclmulqdq", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vpcmpeqb_Vdq_Hdq_Wdq = { "vpcmpeqb", "vpcmpeqb", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpeqd_Vdq_Hdq_Wdq = { "vpcmpeqd", "vpcmpeqd", Vdq, Hdq, Wdq, XX, IA_AVX },
@ -1465,10 +1477,15 @@ Ia_vpcmpgtw_Vdq_Hdq_Wdq = { "vpcmpgtw", "vpcmpgtw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpcmpistri_Vdq_Wdq_Ib = { "vpcmpistri", "vpcmpistri", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vpcmpistrm_Vdq_Wdq_Ib = { "vpcmpistrm", "vpcmpistrm", Vdq, Wdq, Ib, XX, IA_AVX },
Ia_vperm2f128_Vdq_Hdq_Wdq_Ib = { "vperm2f128", "vperm2f128", Vdq, Hdq, Wdq, Ib, IA_AVX },
Ia_vperm2i128_Vdq_Hdq_Wdq_Ib = { "vperm2128", "vperm2i128", Vdq, Hdq, Wdq, Ib, IA_AVX2 },
Ia_vpermd_Vdq_Hdq_Wdq = { "vpermd", "vpermd", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpermilpd_Vpd_Hpd_Wpd = { "vpermilpd", "vpermilpd", Vpd, Hpd, Wpd, XX, IA_AVX },
Ia_vpermilpd_Vpd_Wpd_Ib = { "vpermilpd", "vpermilpd", Vpd, Wpd, Ib, XX, IA_AVX },
Ia_vpermilps_Vps_Hps_Wps = { "vpermilps", "vpermilps", Vps, Hps, Wps, XX, IA_AVX },
Ia_vpermilps_Vps_Wps_Ib = { "vpermilps", "vpermilps", Vps, Wps, Ib, XX, IA_AVX },
Ia_vpermpd_Vpd_Wpd_Ib = { "vpermpd", "vpermpd", Vpd, Wpd, Ib, XX, IA_AVX2 },
Ia_vpermps_Vps_Hps_Wps = { "vpermps", "vpermps", Vps, Hps, Wps, XX, IA_AVX2 },
Ia_vpermq_Vdq_Wdq_Ib = { "vpermq", "vpermq", Vdq, Wdq, Ib, XX, IA_AVX2 },
Ia_vpextrb_Ebd_Vdq_Ib = { "vpextrb", "vpextrb", Ebd, Vdq, Ib, XX, IA_AVX },
Ia_vpextrd_Ed_Vdq_Ib = { "vpextrd", "vpextrd", Ed, Vdq, Ib, XX, IA_AVX },
Ia_vpextrq_Eq_Vdq_Ib = { "vpextrq", "vpextrq", Eq, Vdq, Ib, XX, IA_AVX },
@ -1533,10 +1550,13 @@ Ia_vpslld_Vdq_Hdq_Wdq = { "vpslld", "vpslld", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpslldq_Hdq_Udq_Ib = { "vpslldq", "vpslldq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllq_Hdq_Udq_Ib = { "vpsllq", "vpsllq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllq_Vdq_Hdq_Wdq = { "vpsllq", "vpsllq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsllvd_Vdq_Hdq_Wdq = { "vpsllvd", "vpsllvd", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpsllvq_Vdq_Hdq_Wdq = { "vpsllvq", "vpsllvq", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpsllw_Hdq_Udq_Ib = { "vpsllw", "vpsllw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsllw_Vdq_Hdq_Wdq = { "vpsllw", "vpsllw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrad_Hdq_Udq_Ib = { "vpsrad", "vpsrad", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrad_Vdq_Hdq_Wdq = { "vpsrad", "vpsrad", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsravd_Vdq_Hdq_Wdq = { "vpsravd", "vpsravd", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpsraw_Hdq_Udq_Ib = { "vpsraw", "vpsraw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsraw_Vdq_Hdq_Wdq = { "vpsraw", "vpsraw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrld_Hdq_Udq_Ib = { "vpsrld", "vpsrld", Hdq, Udq, Ib, XX, IA_AVX },
@ -1544,6 +1564,8 @@ Ia_vpsrld_Vdq_Hdq_Wdq = { "vpsrld", "vpsrld", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrldq_Hdq_Udq_Ib = { "vpsrldq", "vpsrldq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlq_Hdq_Udq_Ib = { "vpsrlq", "vpsrlq", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlq_Vdq_Hdq_Wdq = { "vpsrlq", "vpsrlq", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsrlvd_Vdq_Hdq_Wdq = { "vpsrlvd", "vpsrlvd", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpsrlvq_Vdq_Hdq_Wdq = { "vpsrlvq", "vpsrlvq", Vdq, Hdq, Wdq, XX, IA_AVX2 },
Ia_vpsrlw_Hdq_Udq_Ib = { "vpsrlw", "vpsrlw", Hdq, Udq, Ib, XX, IA_AVX },
Ia_vpsrlw_Vdq_Hdq_Wdq = { "vpsrlw", "vpsrlw", Vdq, Hdq, Wdq, XX, IA_AVX },
Ia_vpsubb_Vdq_Hdq_Wdq = { "vpsubb", "vpsubb", Vdq, Hdq, Wdq, XX, IA_AVX },