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Fix PEXTRB/PEXTRW/PEXTRD/EXTRACTPS

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This commit is contained in:
Stanislav Shwartsman 2010-04-02 19:01:17 +00:00
parent caa30e3462
commit 69517f9143
5 changed files with 29 additions and 55 deletions
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26
bochs/disasm/dis_groups.cc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dis_groups.cc,v 1.51 2010-03-26 10:39:40 sshwarts Exp $
// $Id: dis_groups.cc,v 1.52 2010-04-02 19:01:16 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
@ -181,38 +181,22 @@ void disassembler::Ey(const x86_insn *insn)
else Ed(insn);
}
void disassembler::Hbd(const x86_insn *insn)
void disassembler::Ebd(const x86_insn *insn)
{
if (insn->mod == 3)
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
dis_sprintf("%s", general_32bit_regname[insn->rm]);
else
(this->*resolve_modrm)(insn, B_SIZE);
}
void disassembler::Hwd(const x86_insn *insn)
void disassembler::Ewd(const x86_insn *insn)
{
if (insn->mod == 3)
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
dis_sprintf("%s", general_32bit_regname[insn->rm]);
else
(this->*resolve_modrm)(insn, W_SIZE);
}
void disassembler::Hd(const x86_insn *insn)
{
if (insn->mod == 3)
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
else
(this->*resolve_modrm)(insn, D_SIZE);
}
void disassembler::Hq(const x86_insn *insn)
{
if (insn->mod == 3)
dis_sprintf("%s", general_32bit_regname[insn->nnn]);
else
(this->*resolve_modrm)(insn, Q_SIZE);
}
// general purpose register
void disassembler::Gb(const x86_insn *insn)
{

19
bochs/disasm/dis_tables.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dis_tables.h,v 1.44 2010-03-26 10:39:40 sshwarts Exp $
// $Id: dis_tables.h,v 1.45 2010-04-02 19:01:16 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2010 Stanislav Shwartsman
@ -85,11 +85,13 @@
#define ERX &disassembler::ERX
#define RRX &disassembler::RRX
#define Eb &disassembler::Eb
#define Ew &disassembler::Ew
#define Ed &disassembler::Ed
#define Eq &disassembler::Eq
#define Ey &disassembler::Ey
#define Eb &disassembler::Eb
#define Ew &disassembler::Ew
#define Ed &disassembler::Ed
#define Eq &disassembler::Eq
#define Ey &disassembler::Ey
#define Ebd &disassembler::Ebd
#define Ewd &disassembler::Ewd
#define Gb &disassembler::Gb
#define Gw &disassembler::Gw
@ -97,11 +99,6 @@
#define Gq &disassembler::Gq
#define Gy &disassembler::Gy
#define Hbd &disassembler::Hbd
#define Hwd &disassembler::Hwd
#define Hd &disassembler::Hd
#define Hq &disassembler::Hq
#define I1 &disassembler::I1
#define Ib &disassembler::Ib
#define Iw &disassembler::Iw

14
bochs/disasm/dis_tables_sse.inc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: dis_tables_sse.inc,v 1.7 2010-03-26 10:39:40 sshwarts Exp $
// $Id: dis_tables_sse.inc,v 1.8 2010-04-02 19:01:16 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2010 Stanislav Shwartsman
@ -1068,9 +1068,9 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a0f[4] = {
};
static BxDisasmOpcodeTable_t BxDisasmGrpOs64B_pextr[3] = {
/* 16 */ { 0, &Ia_pextrd_Hd_Udq_Ib },
/* 32 */ { 0, &Ia_pextrd_Hd_Udq_Ib },
/* 64 */ { 0, &Ia_pextrq_Hq_Udq_Ib },
/* 16 */ { 0, &Ia_pextrd_Ed_Vdq_Ib },
/* 32 */ { 0, &Ia_pextrd_Ed_Vdq_Ib },
/* 64 */ { 0, &Ia_pextrq_Eq_Vdq_Ib },
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f3a16[4] = {
@ -1379,10 +1379,10 @@ static BxDisasmOpcodeTable_t BxDisasm3ByteOpTable0f3a[256] = {
/* 11 */ { 0, &Ia_Invalid },
/* 12 */ { 0, &Ia_Invalid },
/* 13 */ { 0, &Ia_Invalid },
/* 14 */ { GRPSSE66(Ia_pextrb_Hbd_Udq_Ib) },
/* 15 */ { GRPSSE66(Ia_pextrw_Hwd_Udq_Ib) },
/* 14 */ { GRPSSE66(Ia_pextrb_Ebd_Vdq_Ib) },
/* 15 */ { GRPSSE66(Ia_pextrw_Ewd_Vdq_Ib) },
/* 16 */ { GRPSSE(0f3a16) },
/* 17 */ { GRPSSE66(Ia_extractps_Hd_Udq_Ib) },
/* 17 */ { GRPSSE66(Ia_extractps_Ed_Vdq_Ib) },
/* 18 */ { 0, &Ia_Invalid },
/* 19 */ { 0, &Ia_Invalid },
/* 1A */ { 0, &Ia_Invalid },

13
bochs/disasm/disasm.h
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: disasm.h,v 1.60 2010-03-30 18:12:19 sshwarts Exp $
// $Id: disasm.h,v 1.61 2010-04-02 19:01:17 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
@ -331,10 +331,6 @@ public:
* selects a general register.
* F - Flags Register.
* G - The reg field of the ModR/M byte selects a general register.
* H - A ModR/M byte follows the opcode and specifies the operand. The
* operand is either a general-purpose register or a memory address.
* In case of the register operand, the reg field of the ModR/M byte
* selects a general register.
* I - Immediate data. The operand value is encoded in subsequent bytes of
* the instruction.
* J - The instruction contains a relative offset to be added to the
@ -449,6 +445,8 @@ public:
void Ed(const x86_insn *insn);
void Eq(const x86_insn *insn);
void Ey(const x86_insn *insn);
void Ebd(const x86_insn *insn);
void Ewd(const x86_insn *insn);
// general purpose register
void Gb(const x86_insn *insn);
@ -457,11 +455,6 @@ public:
void Gq(const x86_insn *insn);
void Gy(const x86_insn *insn);
void Hbd(const x86_insn *insn);
void Hwd(const x86_insn *insn);
void Hd(const x86_insn *insn);
void Hq(const x86_insn *insn);
// immediate
void I1(const x86_insn *insn);
void Ib(const x86_insn *insn);

12
bochs/disasm/opcodes.inc
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@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: opcodes.inc,v 1.37 2010-03-30 18:12:19 sshwarts Exp $
// $Id: opcodes.inc,v 1.38 2010-04-02 19:01:17 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2009 Stanislav Shwartsman
@ -291,7 +291,7 @@ Ia_dpps_Vps_Wps_Ib = { "dpps", "dpps", Vps, Wps, Ib, XX, IA_SSE4_1 },
Ia_emms = { "emms", "emms", XX, XX, XX, XX, IA_MMX },
Ia_enter = { "enter", "enter", IwIb, XX, XX, XX, 0 },
Ia_error = { "(error)", "(error)", XX, XX, XX, XX, 0 },
Ia_extractps_Hd_Udq_Ib = { "extractps", "extractps", Hd, Udq, Ib, XX, IA_SSE4_1 },
Ia_extractps_Ed_Vdq_Ib = { "extractps", "extractps", Ed, Vdq, Ib, XX, IA_SSE4_1 },
Ia_extrq_Vdq_IbIb = { "extrq", "extrq", Vdq, IbIb, XX, XX, IA_SSE4A },
Ia_extrq_Vdq_Udq = { "extrq", "extrq", Vdq, Udq, XX, XX, IA_SSE4A },
Ia_f2xm1 = { "f2xm1", "f2xm1", XX, XX, XX, XX, IA_X87 },
@ -827,12 +827,12 @@ Ia_pcmpgtw_Pq_Qq = { "pcmpgtw", "pcmpgtw", Pq, Qq, XX, XX, IA_MMX },
Ia_pcmpgtw_Vdq_Wdq = { "pcmpgtw", "pcmpgtw", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_pcmpistri_Vdq_Wdq_Ib = { "pcmpistri", "pcmpistri", Vdq, Wdq, Ib, XX, IA_SSE4_2 },
Ia_pcmpistrm_Vdq_Wdq_Ib = { "pcmpistrm", "pcmpistrm", Vdq, Wdq, Ib, XX, IA_SSE4_2 },
Ia_pextrb_Hbd_Udq_Ib = { "pextrb", "pextrb", Hbd, Udq, Ib, XX, IA_SSE4_1 },
Ia_pextrd_Hd_Udq_Ib = { "pextrd", "pextrd", Hd, Udq, Ib, XX, IA_SSE4_1 },
Ia_pextrq_Hq_Udq_Ib = { "pextrq", "pextrq", Hq, Udq, Ib, XX, IA_SSE4_1 },
Ia_pextrb_Ebd_Vdq_Ib = { "pextrb", "pextrb", Ebd, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrd_Ed_Vdq_Ib = { "pextrd", "pextrd", Ed, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrq_Eq_Vdq_Ib = { "pextrq", "pextrq", Eq, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrw_Ewd_Vdq_Ib = { "pextrw", "pextrw", Ewd, Vdq, Ib, XX, IA_SSE4_1 },
Ia_pextrw_Gd_Nq_Ib = { "pextrw", "pextrw", Gd, Nq, Ib, XX, IA_3DNOW | IA_SSE },
Ia_pextrw_Gd_Udq_Ib = { "pextrw", "pextrw", Gd, Udq, Ib, XX, IA_SSE2 },
Ia_pextrw_Hwd_Udq_Ib = { "pextrw", "pextrw", Hwd, Udq, Ib, XX, IA_SSE4_1 },
Ia_pf2id_Pq_Qq = { "pf2id", "pf2id", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pf2iw_Pq_Qq = { "pf2iw", "pf2iw", Pq, Qq, XX, XX, IA_3DNOW },
Ia_pfacc_Pq_Qq = { "pfacc", "pfacc", Pq, Qq, XX, XX, IA_3DNOW },