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AMD released new Vol4: 128 and 256 bit vector instructions, dropped SSE4A

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This commit is contained in:
Stanislav Shwartsman 2011-05-30 20:15:50 +00:00
parent 1ba77b9f10
commit 04e9254e2c
10 changed files with 64 additions and 77 deletions
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27
bochs/cpu/cpu.h
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@ -620,20 +620,19 @@ typedef struct
#define BX_CPU_SSSE3 (1 << 12) /* SSSE3 instruction */
#define BX_CPU_SSE4_1 (1 << 13) /* SSE4_1 instruction */
#define BX_CPU_SSE4_2 (1 << 14) /* SSE4_2 instruction */
#define BX_CPU_SSE4A (1 << 15) /* SSE4A instruction */
#define BX_CPU_MONITOR_MWAIT (1 << 16) /* MONITOR/MWAIT instruction */
#define BX_CPU_VMX (1 << 17) /* VMX instruction */
#define BX_CPU_SMX (1 << 18) /* SMX instruction */
#define BX_CPU_SVM (1 << 19) /* SVM instruction */
#define BX_CPU_XSAVE (1 << 20) /* XSAVE/XRSTOR extensions instruction */
#define BX_CPU_XSAVEOPT (1 << 21) /* XSAVEOPT instruction */
#define BX_CPU_AES_PCLMULQDQ (1 << 22) /* AES+PCLMULQDQ instruction */
#define BX_CPU_MOVBE (1 << 23) /* MOVBE Intel Atom(R) instruction */
#define BX_CPU_FSGSBASE (1 << 24) /* FS/GS BASE access instruction */
#define BX_CPU_AVX (1 << 25) /* AVX instruction */
#define BX_CPU_AVX_F16C (1 << 26) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (1 << 27) /* AVX FMA instruction */
#define BX_CPU_X86_64 (1 << 28) /* x86-64 instruction */
#define BX_CPU_MONITOR_MWAIT (1 << 15) /* MONITOR/MWAIT instruction */
#define BX_CPU_VMX (1 << 16) /* VMX instruction */
#define BX_CPU_SMX (1 << 17) /* SMX instruction */
#define BX_CPU_SVM (1 << 18) /* SVM instruction */
#define BX_CPU_XSAVE (1 << 19) /* XSAVE/XRSTOR extensions instruction */
#define BX_CPU_XSAVEOPT (1 << 20) /* XSAVEOPT instruction */
#define BX_CPU_AES_PCLMULQDQ (1 << 21) /* AES+PCLMULQDQ instruction */
#define BX_CPU_MOVBE (1 << 22) /* MOVBE Intel Atom(R) instruction */
#define BX_CPU_FSGSBASE (1 << 23) /* FS/GS BASE access instruction */
#define BX_CPU_AVX (1 << 24) /* AVX instruction */
#define BX_CPU_AVX_F16C (1 << 25) /* AVX F16 convert instruction */
#define BX_CPU_AVX_FMA (1 << 26) /* AVX FMA instruction */
#define BX_CPU_X86_64 (1 << 27) /* x86-64 instruction */
// cpuid non-ISA features
#define BX_CPU_DEBUG_EXTENSIONS (1 << 0) /* Debug Extensions support */

2
bochs/cpu/cpuid.cc
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@ -363,7 +363,7 @@ Bit32u BX_CPU_C::get_ext2_cpuid_features(void)
// [3:3] Extended APIC Space
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
// [5:5] LZCNT: LZCNT instruction support
// [6:6] SSE4A: SSE4A Instructions support
// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
// [7:7] Misaligned SSE support
// [8:8] PREFETCHW: PREFETCHW instruction support
// [9:9] OSVW: OS visible workarounds (AMD)

2
bochs/cpu/cpuid.h
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@ -220,7 +220,7 @@ struct cpuid_function_t {
// [3:3] Extended APIC Space
// [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8
// [5:5] LZCNT: LZCNT instruction support
// [6:6] SSE4A: SSE4A Instructions support
// [6:6] SSE4A: SSE4A Instructions support (deprecated?)
// [7:7] Misaligned SSE support
// [8:8] PREFETCHW: PREFETCHW instruction support
// [9:9] OSVW: OS visible workarounds (AMD)

2
bochs/cpu/paging.cc
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@ -529,7 +529,9 @@ void BX_CPU_C::page_fault(unsigned fault, bx_address laddr, unsigned user, unsig
#define BX_LEVEL_PDE 1
#define BX_LEVEL_PTE 0
#if BX_SUPPORT_X86_64 || BX_DEBUGGER
static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" };
#endif
#if BX_CPU_LEVEL >= 6

2
bochs/cpu/todo
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@ -49,4 +49,4 @@ TODO (know issues in CPU model):
- Dual-monitor treatment of SMIs and SMM not implemented yet
- VMENTER to not-active state not supported yet
[!] SSE4A, SMX, SVM, XOP
[!] SMX, SVM, XOP

10
bochs/disasm/dis_groups.cc
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@ -462,7 +462,7 @@ void disassembler::Wdq(const x86_insn *insn)
{
if (insn->mod == 3) Udq(insn);
else
(this->*resolve_modrm)(insn, O_SIZE);
(this->*resolve_modrm)(insn, XMM_SIZE + insn->vex_vl);
}
void disassembler::Wsd(const x86_insn *insn) { Wq(insn); }
@ -521,9 +521,9 @@ void disassembler::Md(const x86_insn *insn) { OP_M(insn, D_SIZE); }
void disassembler::Mq(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
void disassembler::Mt(const x86_insn *insn) { OP_M(insn, T_SIZE); }
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, O_SIZE); }
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, O_SIZE); }
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, O_SIZE); }
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_vl); }
void disassembler::Mss(const x86_insn *insn) { OP_M(insn, D_SIZE); }
void disassembler::Msd(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
@ -615,7 +615,7 @@ void disassembler::OP_sY(const x86_insn *insn, unsigned size)
}
void disassembler::sYq(const x86_insn *insn) { OP_sY(insn, Q_SIZE); }
void disassembler::sYdq(const x86_insn *insn) { OP_sY(insn, O_SIZE); }
void disassembler::sYdq(const x86_insn *insn) { OP_sY(insn, XMM_SIZE + insn->vex_vl); }
#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))

31
bochs/disasm/dis_tables_sse.inc
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@ -121,8 +121,8 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2a[4] = {
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2b[4] = {
/* -- */ { 0, &Ia_movntps_Mps_Vps },
/* 66 */ { 0, &Ia_movntpd_Mpd_Vpd },
/* F3 */ { 0, &Ia_movntss_Mss_Vss }, // SSE4A
/* F2 */ { 0, &Ia_movntsd_Msd_Vsd } // SSE4A
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f2c[4] = {
@ -398,43 +398,32 @@ static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f76[4] = {
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupRmEXTRQ[8] = {
/* 0 */ { 0, &Ia_extrq_Vdq_IbIb },
/* 1 */ { 0, &Ia_Invalid },
/* 2 */ { 0, &Ia_Invalid },
/* 3 */ { 0, &Ia_Invalid },
/* 4 */ { 0, &Ia_Invalid },
/* 5 */ { 0, &Ia_Invalid },
/* 6 */ { 0, &Ia_Invalid },
/* 7 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f78[4] = {
/* -- */ { 0, &Ia_vmread_Ed_Gd }, // VMX
/* 66 */ { GRPRM(EXTRQ) }, // SSE4A
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_insertq_Vdq_Udq_IbIb }, // SSE4A
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f78Q[4] = {
/* -- */ { 0, &Ia_vmread_Eq_Gq }, // VMX
/* 66 */ { GRPRM(EXTRQ) }, // SSE4A
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_insertq_Vdq_Udq_IbIb } // SSE4A
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f79[4] = {
/* -- */ { 0, &Ia_vmwrite_Gd_Ed }, // VMX
/* 66 */ { 0, &Ia_extrq_Vdq_Udq }, // SSE4A
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_insertq_Vdq_Udq } // SSE4A
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f79Q[4] = {
/* -- */ { 0, &Ia_vmwrite_Gq_Eq }, // VMX
/* 66 */ { 0, &Ia_extrq_Vdq_Udq }, // SSE4A
/* 66 */ { 0, &Ia_Invalid },
/* F3 */ { 0, &Ia_Invalid },
/* F2 */ { 0, &Ia_insertq_Vdq_Udq } // SSE4A
/* F2 */ { 0, &Ia_Invalid }
};
static BxDisasmOpcodeTable_t BxDisasmGroupSSE_0f7c[4] = {

44
bochs/disasm/disasm.h
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@ -54,20 +54,19 @@
#define IA_SSSE3 (1 << 12) /* SSSE3 instruction */
#define IA_SSE4_1 (1 << 13) /* SSE4_1 instruction */
#define IA_SSE4_2 (1 << 14) /* SSE4_2 instruction */
#define IA_SSE4A (1 << 15) /* SSE4A instruction */
#define IA_MONITOR_MWAIT (1 << 16) /* MONITOR/MWAIT instruction */
#define IA_VMX (1 << 17) /* VMX instruction */
#define IA_SMX (1 << 18) /* SMX instruction */
#define IA_SVM (1 << 19) /* SVM instruction */
#define IA_XSAVE (1 << 20) /* XSAVE/XRSTOR extensions instruction */
#define IA_XSAVEOPT (1 << 21) /* XSAVEOPT instruction */
#define IA_AES_PCLMULQDQ (1 << 22) /* AES+PCLMULQDQ instruction */
#define IA_MOVBE (1 << 23) /* MOVBE Intel Atom(R) instruction */
#define IA_FSGSBASE (1 << 24) /* FS/GS BASE access instruction */
#define IA_AVX (1 << 25) /* AVX instruction */
#define IA_AVX_F16C (1 << 26) /* AVX F16 convert instruction */
#define IA_AVX_FMA (1 << 27) /* AVX FMA instruction */
#define IA_X86_64 (1 << 28) /* x86-64 instruction */
#define IA_MONITOR_MWAIT (1 << 15) /* MONITOR/MWAIT instruction */
#define IA_VMX (1 << 16) /* VMX instruction */
#define IA_SMX (1 << 17) /* SMX instruction */
#define IA_SVM (1 << 18) /* SVM instruction */
#define IA_XSAVE (1 << 19) /* XSAVE/XRSTOR extensions instruction */
#define IA_XSAVEOPT (1 << 20) /* XSAVEOPT instruction */
#define IA_AES_PCLMULQDQ (1 << 21) /* AES+PCLMULQDQ instruction */
#define IA_MOVBE (1 << 22) /* MOVBE Intel Atom(R) instruction */
#define IA_FSGSBASE (1 << 23) /* FS/GS BASE access instruction */
#define IA_AVX (1 << 24) /* AVX instruction */
#define IA_AVX_F16C (1 << 25) /* AVX F16 convert instruction */
#define IA_AVX_FMA (1 << 26) /* AVX FMA instruction */
#define IA_X86_64 (1 << 27) /* x86-64 instruction */
/* general purpose bit register */
enum {
@ -120,14 +119,15 @@ struct BxDisasmOpcodeTable_t
#define NO_SEG_OVERRIDE 0xFF
// datasize attributes
#define X_SIZE 0x0000 /* no size */
#define B_SIZE 0x0100 /* byte */
#define W_SIZE 0x0200 /* word */
#define D_SIZE 0x0300 /* double word */
#define Q_SIZE 0x0400 /* quad word */
#define Z_SIZE 0x0500 /* double word in 32-bit mode, quad word in 64-bit mode */
#define O_SIZE 0x0600 /* oct word or double quad word (XMM) */
#define T_SIZE 0x0700 /* 10-byte x87 floating point */
#define X_SIZE 0x0000 /* no size */
#define B_SIZE 0x0100 /* byte */
#define W_SIZE 0x0200 /* word */
#define D_SIZE 0x0300 /* double word */
#define Q_SIZE 0x0400 /* quad word */
#define Z_SIZE 0x0500 /* double word in 32-bit mode, quad word in 64-bit mode */
#define T_SIZE 0x0600 /* 10-byte x87 floating point */
#define XMM_SIZE 0x0700 /* double quad word (XMM) */
#define YMM_SIZE 0x0800 /* quadruple quad word (YMM) */
// branch hint attribute
#define BRANCH_HINT 0x1000

12
bochs/disasm/opcodes.inc
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@ -286,8 +286,6 @@ Ia_emms = { "emms", "emms", XX, XX, XX, XX, IA_MMX },
Ia_enter = { "enter", "enter", IwIb, XX, XX, XX, 0 },
Ia_error = { "(error)", "(error)", XX, XX, XX, XX, 0 },
Ia_extractps_Ed_Vdq_Ib = { "extractps", "extractps", Ed, Vdq, Ib, XX, IA_SSE4_1 },
Ia_extrq_Vdq_IbIb = { "extrq", "extrq", Vdq, IbIb, XX, XX, IA_SSE4A },
Ia_extrq_Vdq_Udq = { "extrq", "extrq", Vdq, Udq, XX, XX, IA_SSE4A },
Ia_f2xm1 = { "f2xm1", "f2xm1", XX, XX, XX, XX, IA_X87 },
Ia_fabs = { "fabs", "fabs", XX, XX, XX, XX, IA_X87 },
Ia_fadd_ST0_STi = { "fadd", "fadd", ST0, STi, XX, XX, IA_X87 },
@ -463,8 +461,6 @@ Ia_inl_EAX_DX = { "in", "inl", EAX_Reg, DX_Reg, XX, XX, 0 },
Ia_inl_EAX_Ib = { "in", "inl", EAX_Reg, Ib, XX, XX, 0 },
Ia_insb_Yb_DX = { "insb", "insb", Yb, DX_Reg, XX, XX, 0 },
Ia_insertps_Vps_Wss_Ib = { "insertps", "insertps", Vps, Wss, Ib, XX, IA_SSE4_1 },
Ia_insertq_Vdq_Udq = { "insertq", "insertq", Vdq, Udq, XX, XX, IA_SSE4A },
Ia_insertq_Vdq_Udq_IbIb = { "insertq", "insertq", Vdq, Udq, IbIb, XX, IA_SSE4A },
Ia_insl_Yd_DX = { "insd", "insl", Yd, DX_Reg, XX, XX, 0 },
Ia_insw_Yw_DX = { "insw", "insw", Yw, DX_Reg, XX, XX, 0 },
Ia_int_Ib = { "int", "int", Ib, XX, XX, XX, 0 },
@ -656,8 +652,6 @@ Ia_movntiq_Mq_Gq = { "movntiq", "movntiq", Mq, Gq, XX, XX, IA_X86_64 },
Ia_movntpd_Mpd_Vpd = { "movntpd", "movntpd", Mpd, Vpd, XX, XX, IA_SSE2 },
Ia_movntps_Mps_Vps = { "movntps", "movntps", Mps, Vps, XX, XX, IA_SSE },
Ia_movntq_Mq_Pq = { "movntq", "movntq", Mq, Pq, XX, XX, IA_3DNOW | IA_SSE },
Ia_movntsd_Msd_Vsd = { "movntsd", "movntsd", Msd, Vsd, XX, XX, IA_SSE4A },
Ia_movntss_Mss_Vss = { "movntss", "movntss", Mss, Vss, XX, XX, IA_SSE4A },
Ia_movq_Cq_Rq = { "mov", "movq", Cq, Rq, XX, XX, IA_X86_64 },
Ia_movq_Dq_Rq = { "mov", "movq", Dq, Rq, XX, XX, IA_X86_64 },
Ia_movq_Eq_Gq = { "mov", "movq", Eq, Gq, XX, XX, IA_X86_64 },
@ -915,9 +909,9 @@ Ia_pmuludq_Pq_Qq = { "pmuludq", "pmuludq", Pq, Qq, XX, XX, IA_SSE2 },
Ia_pmuludq_Vdq_Wdq = { "pmuludq", "pmuludq", Vdq, Wdq, XX, XX, IA_SSE2 },
Ia_popal = { "popad", "popal", XX, XX, XX, XX, 0 },
Ia_popaw = { "popa", "popa", XX, XX, XX, XX, 0 },
Ia_popcnt_Gd_Ed = { "popcnt", "popcnt", Gd, Ed, XX, XX, IA_SSE4_2 | IA_SSE4A },
Ia_popcnt_Gq_Eq = { "popcnt", "popcnt", Gq, Eq, XX, XX, IA_SSE4_2 | IA_SSE4A | IA_X86_64 },
Ia_popcnt_Gw_Ew = { "popcnt", "popcnt", Gw, Ew, XX, XX, IA_SSE4_2 | IA_SSE4A },
Ia_popcnt_Gd_Ed = { "popcnt", "popcnt", Gd, Ed, XX, XX, IA_SSE4_2 },
Ia_popcnt_Gq_Eq = { "popcnt", "popcnt", Gq, Eq, XX, XX, IA_SSE4_2 | IA_X86_64 },
Ia_popcnt_Gw_Ew = { "popcnt", "popcnt", Gw, Ew, XX, XX, IA_SSE4_2 },
Ia_popfl = { "popfd", "popfl", XX, XX, XX, XX, 0 },
Ia_popfq = { "popfq", "popfq", XX, XX, XX, XX, IA_X86_64 },
Ia_popfw = { "popf", "popf", XX, XX, XX, XX, 0 },

9
bochs/disasm/resolve.cc
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@ -338,12 +338,15 @@ void disassembler::print_datasize(unsigned size)
case Q_SIZE:
dis_sprintf("qword ptr ");
break;
case O_SIZE:
dis_sprintf("dqword ptr ");
break;
case T_SIZE:
dis_sprintf("tbyte ptr ");
break;
case XMM_SIZE:
dis_sprintf("dqword ptr ");
break;
case YMM_SIZE:
dis_sprintf("qqword ptr ");
break;
case X_SIZE:
break;
};