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2607 Commits

Author SHA1 Message Date
Stanislav Shwartsman
75bda1d5cd implemented SVM emulation support for Bochs (incomplete yet) 
I am merging the code in order to start making shortcuts between VMX emulation and SVM emulation.
Of course SVM emulation is incomplete, completely untested and not expected to work.
But someone could already take a look one the code and give some suggestions.

Also looking for anybody with existing SVM kernels - as simple as possible - for testing.

Status:
 - exceptions intercept is not implemented yet
 - IO intercept is not implemented yet
 - MSR intercept is not implemented yet
 - virtual interrupts are not implemented yet
 - CPUID is not implemented yet

No advanced SVM featurez planned - I am implementing the very basic 'Pacifica' document from 2005 using QEMU code as reference.
 2011-12-25 19:35:29 +00:00
Stanislav Shwartsman
2dee4b12be added VMX .bochsrc option to ctoggle VMX ON/OFF on runtime 2011-12-21 09:11:51 +00:00
Stanislav Shwartsman
e7ed8aca5c move inhibit interrrupts functionality to icount interface 2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
7cdeecf198 VMX: fixed VirtualBox VMX guest Guru Meditation - FS.BASE get corrupted after saving/restoring unusable selector 2011-12-19 16:06:53 +00:00
Stanislav Shwartsman
6cc03432d9 improve VMX debug print 2011-12-18 21:04:30 +00:00
Stanislav Shwartsman
f6203dae7d instrumentation: added special indication for indirect call/jump 2011-12-18 18:11:56 +00:00
Stanislav Shwartsman
9763643106 VMX: Fixed VMFUNC instruction behavior to align with Intel SDM revision 041 2011-12-17 14:06:23 +00:00
Stanislav Shwartsman
cbbd8bfd46 fixed some warnings after compilation with msvcpp 2010 2011-12-10 18:58:25 +00:00
Stanislav Shwartsman
ac0ebc9728 added debug prints about vmcs initialization 2011-12-09 19:57:40 +00:00
Stanislav Shwartsman
f496e78326 fixed compilation warning 2011-12-02 19:40:31 +00:00
Stanislav Shwartsman
1e3e6ff2af BMI: fixed EFLAGS after BMI instructions (set EFLAGS while preserving PF was not implemented properly in 2.5 release) 2011-11-29 19:50:26 +00:00
Stanislav Shwartsman
b8f2d91b9a fixed compilation err 2011-11-28 21:16:40 +00:00
Stanislav Shwartsman
99bec5155e fixed compilation err in instrumentation module 2011-11-28 10:08:03 +00:00
Stanislav Shwartsman
8cb359fab5 fixed flags handling for BMI instructions 2011-11-27 13:23:26 +00:00
Stanislav Shwartsman
100622e958 fix ULL suffix for 64bit int, use BX_CONST64 instead 2011-11-26 19:01:53 +00:00
Stanislav Shwartsman
f09bdf353a RDMSR can also read TSC so make it end-of-trace as well (same as RDTSC) 2011-11-24 16:03:51 +00:00
Stanislav Shwartsman
f660d3dc68 implemented missed XOP instructions FRCZPS/PD/SS/SD + update CHANGES with fixed bugs 2011-11-24 11:34:26 +00:00
Stanislav Shwartsman
c74f590077 implemented TSC-Deadline APIC timer mode 2011-11-21 12:51:50 +00:00
Stanislav Shwartsman
e4bd200119 do not report TSC Deadline for Sandy Bridge CPUID - not implemented yet 2011-11-20 18:25:39 +00:00
Stanislav Shwartsman
9be8552b80 - Implemented VM Functions support and EPTP-Switching VM Functions 
- Added VMEXIT conditions for INVPCID instruction

Now Bochs is fully aligned with latest pulished Intel's SDM rev040.
 2011-11-05 07:31:51 +00:00
Stanislav Shwartsman
42a0a178eb disasm for XOP instructions 2011-10-30 08:58:49 +00:00
Stanislav Shwartsman
ad9bdbe550 fixed compilation failure 2011-10-21 08:06:55 +00:00
Stanislav Shwartsman
b1a6b34616 implemented PERMIL2PS/PERMIL2PD XOP instructions 2011-10-20 17:37:57 +00:00
Stanislav Shwartsman
ddecc0234a fixed (c) info 2011-10-20 14:06:12 +00:00
Stanislav Shwartsman
3035fcd0af implemented XOP FMADCSWD/FMADCSSWD instructions 2011-10-20 13:55:26 +00:00
Stanislav Shwartsman
5d9bbae71c bugfix: cant use ib2 it is overlap with disp32 2011-10-19 21:28:36 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
314171bb56 fixed compilation w/o AVX 2011-10-09 13:56:39 +00:00
Stanislav Shwartsman
71cbff104b fixing xsave/xrstor flows with AVX 2011-10-09 09:19:49 +00:00
Stanislav Shwartsman
8ada4ce5e4 added to cpudb: Intel(R) Core(TM) i5 M 520 (Arrandale) - based on Westmere arch 2011-10-07 19:32:44 +00:00
Stanislav Shwartsman
2580d8c46d added FMA4 AMD instructions support, fixed mem access length for Intel scalar FMA instructions 2011-10-07 14:09:35 +00:00
Stanislav Shwartsman
aad57310c2 disasm for FMA4, better dbg print SSE rounding control with MXCSR 2011-10-06 20:33:10 +00:00
Stanislav Shwartsman
8a9b8f4622 MXCSR.FUZ is ignoired for F16 instructions 2011-10-03 15:08:22 +00:00
Stanislav Shwartsman
e282b5e88d Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code 
Fix decoding of opcodes with VEX.W=1 in 32-bit mode (AVX2, FMA)
 2011-10-01 15:40:36 +00:00
Stanislav Shwartsman
f425400af5 fixed warnings from compilation with mingw-gcc 4.6.1 2011-09-30 20:38:18 +00:00
Stanislav Shwartsman
e5d0540365 commit new added files 2011-09-29 22:38:38 +00:00
Stanislav Shwartsman
6751af5d8e added AVX FMA extensions support. The implementation is based on QEMU patch by Peter Maydell (fixed) 2011-09-29 22:20:56 +00:00
Stanislav Shwartsman
275194fb32 #GP on reading VMX_EPT_VPID_CAP MSR when EPT and VPID disabled 2011-09-26 20:36:26 +00:00
Stanislav Shwartsman
f0d9f8fab7 added some comments 2011-09-26 20:10:15 +00:00
Stanislav Shwartsman
0547c8823e compilation w/o x86-64 2011-09-26 19:48:58 +00:00
Stanislav Shwartsman
12ad45395b enable Penryn VMX capabilities with VMX=1, VMX=2 is required for EPT and heavier stuff 2011-09-26 19:36:20 +00:00
Stanislav Shwartsman
54d1d8aa55 added new assertion to generic cpuid 2011-09-26 18:47:47 +00:00
Stanislav Shwartsman
aa96ecd98a compilation fix 2011-09-26 18:18:10 +00:00
Stanislav Shwartsman
0aadf88c07 more polishing for vmx configurability 2011-09-26 18:08:31 +00:00
Stanislav Shwartsman
c28c7f6a06 Supply real VMX capabilities together with the CPU MODEL .bochsrc option. 
So now the same single option will choose not only the CPUID flags but also VMX capabilities matching real HW machine.

Removed cpuid of core2_extreme_x9770 from the cpudb. I don't remember its VMX capabilities anyway.
There is another Penryn model in the cpudb - core2_penryn_t9600.
 2011-09-26 12:31:40 +00:00
Stanislav Shwartsman
8d95830562 first step to configuration of VMX through cpuid_t class 2011-09-25 19:04:55 +00:00
Stanislav Shwartsman
b66feecc86 move common instrumentation constants (valid for all stubs) to cpu.h 2011-09-25 17:38:54 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
2b7894de7b fixed dbg print mentioned in SF bug 3029271 2011-09-22 22:08:18 +00:00
Stanislav Shwartsman
1b9f286945 - New way of CPUs scheduling in SMP mode brings up to 50% speedup to the 
SMP emulation. New implementation uses dynamic CPU quantum value and takes
   full advantage of the trace cache. Each emulated processor will execute
   the whole trace before switching to the next processor.
 * It is also safe to use large (up to 16 instructions) quantum values for
   the SMP emulation now and improve performance even further.

The same merge also completely fixes SF bug :
  [3312237] stepN command might be not working properly

Handlers chaining speedups are also supported with SMP emulation now.
 2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
f81589c5d6 Don't allow traces longer than cpu_loop can execute 2011-09-21 20:28:29 +00:00
Stanislav Shwartsman
c6d07ae1b5 store modrm() for x87 in Ib() byte because x87 have no Ib() 2011-09-20 06:02:27 +00:00
Stanislav Shwartsman
2583f8549a small code duplication fix 2011-09-19 20:47:59 +00:00
Stanislav Shwartsman
d489ba3d37 generic cpuid: automatically enable lzcnt of bmi is enabled; sse4a support in cpuid 2011-09-18 18:17:34 +00:00
Stanislav Shwartsman
6fb673b9fa change BX_PANIC to BX_ERROR 2011-09-18 17:36:54 +00:00
Stanislav Shwartsman
50207eeb90 - Added support for AMD SSE4A emulation, the instructions can be enabled 
using .bochsrc CPUID option.
 2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
efc588cf1e rename avx2_gather.cc -> gather.cc 2011-09-16 20:59:57 +00:00
Stanislav Shwartsman
ea54f40361 keep global pages when needed in INVPCID/INVVPID 2011-09-16 20:52:38 +00:00
Stanislav Shwartsman
3632340dac improve bochs exit dump in long64 mode 2011-09-16 20:25:05 +00:00
Stanislav Shwartsman
88a58b3781 fixed compilation with x86-64=0 2011-09-16 20:12:36 +00:00
Stanislav Shwartsman
330bf62f61 added INVPCID instruction support 2011-09-16 20:06:23 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
d5fcfabb38 bugfix + update changes 2011-09-13 19:38:09 +00:00
Stanislav Shwartsman
f4dbaf1cd8 re-shuffle macros, no impact in general 2011-09-13 17:55:36 +00:00
Stanislav Shwartsman
02e1a0f23c Merge lazy flags optimization by Darek Mihocka. 
I measure slight but consistent speedup of ~1-3% for all guests.
Tested: Windows XP/7 boot 32/64 bit, various Linux live CD
 2011-09-12 19:36:53 +00:00
Stanislav Shwartsman
9f1f4781b3 fixed Sandy Bridge name in err message - it is Core i7 and not Core2 2011-09-06 19:49:22 +00:00
Stanislav Shwartsman
939aee87c9 handle special case - BSF/BSR vs TZCNT/LZCNT 2011-09-06 19:18:21 +00:00
Stanislav Shwartsman
184837e0ed fixed compilation err with no handlers chaining enabled 2011-09-06 15:41:52 +00:00
Stanislav Shwartsman
96cedbc756 continue handlers-chaining optimization: update time once per trace and not for every instruction 2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
e000b61cfd make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin 2011-09-06 14:13:39 +00:00
Stanislav Shwartsman
5a350143a5 bug fixes 2011-09-06 13:09:45 +00:00
Stanislav Shwartsman
c67338203c small fixups, code cleanup and reorganization 2011-09-05 17:14:49 +00:00
Stanislav Shwartsman
41f9b25777 fixed avx2 gather instructions 2011-09-04 19:50:18 +00:00
Stanislav Shwartsman
c0f5919787 small optimization 2011-09-03 15:36:40 +00:00
Stanislav Shwartsman
8099fd9efd implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8 2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
cf56ffb6e0 BSF/BSR should stay, only F3 prefix change opcode 2011-08-31 21:13:50 +00:00
Stanislav Shwartsman
9d18af1207 fixed compilation for AVX OFF 2011-08-31 20:52:53 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
d2f7351be2 cpu.h cleanup + update msdev workspaces cpudb projects 2011-08-30 22:22:07 +00:00
Stanislav Shwartsman
dfd769a102 - Fixed compilation issue with cpu-level=5 
- SYSCALL/SYSRET: SYSCALL/SYSRET instructions are not supported in legacy mode for Intel processors
- CPUID: CPUID.0x80000001.EDX[11] SYSCALL/SYSRET support should not be reported outside long64 mode if legacy mode SYSCALL/SYSRET is not supported
- Added new CPUDB entry - AMD K6-2 3D proc3essor (Chomper)
 2011-08-30 22:00:27 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
9693bacacb syscall/sysret in legacy mode is supported in k6-2. preparing code to it ... 2011-08-30 20:41:00 +00:00
Stanislav Shwartsman
0f73ff39df bug fix 2011-08-30 19:16:08 +00:00
Stanislav Shwartsman
c30275016e avx2 added broadcast from register 2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
6bdfbeeffa fixed for gather VSIB calculation 2011-08-28 20:14:53 +00:00
Stanislav Shwartsman
239c5a449d added 'locked' information to bxInstruction_c for instrumentation and other future use 2011-08-27 20:09:18 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
d841e82d87 MOVBE instruction exists only in memory form 2011-08-25 21:20:50 +00:00
Stanislav Shwartsman
b3898f4bec small optimization for PALIGNR instruction 2011-08-25 19:29:33 +00:00
Stanislav Shwartsman
5dde2dc744 fixed typo 2011-08-23 21:56:35 +00:00
Stanislav Shwartsman
fa930961c2 small optimization 2011-08-23 21:25:34 +00:00
Stanislav Shwartsman
4fae848888 just rename variable 2011-08-23 20:27:52 +00:00
Stanislav Shwartsman
002e7a3818 MSR_TSC_AUX is not available without RDTSCP 2011-08-21 19:09:35 +00:00
Stanislav Shwartsman
371dc200fc Remove the 'trace' debug feature fro the main stream (which now runs with handlers chaining) and this way reduce each handler size. 
Another 3% speedup on WinXP boot on top of handlers chaining + reduction of Bochs binary size by 45K.
 2011-08-21 17:04:21 +00:00
Stanislav Shwartsman
a5e187189a set max trace length back to 32 2011-08-21 16:44:02 +00:00
Stanislav Shwartsman
1e2e3c8b0e forgot to merge file 2011-08-21 14:38:33 +00:00
Stanislav Shwartsman
13feb0772a - 10% emulation speedup with handlers chaining optimization implemented. The 
feature is enabled by default when configure with --enable-all-optimizations
    option, to disable handlers chaining speedups configure with
        --disable-handlers-chaining
 2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
dd79431702 rename AVX handlers - match their real operands 2011-08-20 15:10:18 +00:00
Volker Ruppert
bfdbf589a0 - removed duplicate 'clean' for cpu/cpudb 
- added missing 'dist-clean' for cpu/cpudb
 2011-08-19 06:31:51 +00:00
Stanislav Shwartsman
542af0dcc1 forgot to add a file 2011-08-18 19:02:16 +00:00
Stanislav Shwartsman
b8b63ac6ea compile CPUDB to separate library 
reduce compile-time dependencies
 2011-08-18 18:55:22 +00:00
Stanislav Shwartsman
30b94b112b regen Makefile.in dep 2011-08-18 05:44:54 +00:00
Stanislav Shwartsman
367e8999d6 fixed leaf 0x7 report in cpuid 2011-08-17 21:33:55 +00:00
Stanislav Shwartsman
ed9b8478b5 undo RDTSC commit 2011-08-17 21:13:06 +00:00
Stanislav Shwartsman
165e6f0fdf separate TSC to uniq feature that can be disabled in CPU configuration 2011-08-17 20:57:44 +00:00
Stanislav Shwartsman
4a3209ae31 Increase cpu param length (exceeded with new icount variable) 
CHECK_MAX_INSTRUCTIONS is not needed for debugger anymore.
Next step: eliminate it for SMP as well and remove cpu_loop parameter.
 2011-08-17 20:00:51 +00:00
Stanislav Shwartsman
b69f728246 Fixed internal debugger part of the bug: 
#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
 2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
86d042a46e added AVX to msdev workspaces 2011-08-16 20:44:02 +00:00
Stanislav Shwartsman
b0d7ffeb90 fixed compilation 2011-08-16 20:07:34 +00:00
Stanislav Shwartsman
a03e0266fb added yonah CPUID to cpudb. remove bxversion.h from dep files 2011-08-16 19:58:56 +00:00
Stanislav Shwartsman
0bc93fdc59 added pentium mmx to cpudb. for now only can be enabled when cpu-level=5 2011-08-16 19:04:36 +00:00
Stanislav Shwartsman
6606c62439 cr4 available since Pentium only 2011-08-16 16:49:04 +00:00
Stanislav Shwartsman
e50e187128 #GP on EFER access when not supported 2011-08-14 20:41:46 +00:00
Stanislav Shwartsman
35ec48d17d small fixes 2011-08-13 18:39:17 +00:00
Stanislav Shwartsman
290d3bf6ad typofix 2011-08-12 18:09:24 +00:00
Stanislav Shwartsman
8962cfddde re-definition of x86-64 support, 1st step towards x86-64 enable/disable through .bochsrc 2011-08-12 18:04:56 +00:00
Stanislav Shwartsman
7af5dccdcf fixed compilation issue 2011-08-11 19:45:21 +00:00
Stanislav Shwartsman
d0344a1b84 added Id Revision to new files 2011-08-11 18:17:45 +00:00
Stanislav Shwartsman
6344c6a719 Added P2 Klamath CPUID + some code reorg again 2011-08-11 18:06:09 +00:00
Stanislav Shwartsman
f15bc6cf75 support for NX outside of x86-64. 
required for Intel Yonah processor which is another interesting CPUID to be added
also found Via C7 CPUID, looking for the way to add it too
 2011-08-10 22:04:33 +00:00
Stanislav Shwartsman
1b27438146 cleanups + small code reorg 2011-08-10 20:31:29 +00:00
Stanislav Shwartsman
360481b391 infastructure for RDMSR/WRMSR control for cpuid class 
now the order is going to be:

1. MSRs emulated in Bochs (msr.cc)
2. MSRs emulated in model specific derivative class of cpuid_t
3. MSR can be loaded from msrs.def file
4. MSR is not found. We can fault or ignore based on ignore_bad_msrs option
 2011-08-09 22:11:56 +00:00
Stanislav Shwartsman
0171324877 small favor to VMX OFF for code that compiled with VMX ON 
avoid function call when not in vmx guest.
 2011-08-09 20:50:51 +00:00
Stanislav Shwartsman
17a94fc58e warning fixes 2011-08-09 18:00:19 +00:00
Stanislav Shwartsman
c6c94a79da dos2unix for generic_cpuid.cc 
fixed xsave leaf CPUID (again)
added one more CPUID configuration: Intel Mobile Core 2 Duo T9600
 2011-08-08 18:20:29 +00:00
Stanislav Shwartsman
4476dea8f8 remove redundant code 2011-08-08 05:47:49 +00:00
Stanislav Shwartsman
20becdfbe7 fix compilation errors 2011-08-05 07:22:43 +00:00
Stanislav Shwartsman
2ee0029749 extract ffxsr support to separate CPU feature 2011-08-04 19:02:49 +00:00
Stanislav Shwartsman
b6e37b818d small changes 2011-08-04 17:35:08 +00:00
Stanislav Shwartsman
1068b4bd8c cleanup 2011-08-03 21:46:46 +00:00
Stanislav Shwartsman
5ffb201184 fixed CPU leaf 0xD 2011-08-03 21:23:08 +00:00
Stanislav Shwartsman
1adda7bf64 Fixed MWAIT leaf CPUID - required for Fedora15 startup 2011-08-03 20:29:24 +00:00
Stanislav Shwartsman
5451be2676 remove duplicated code 2011-08-03 18:09:07 +00:00
Stanislav Shwartsman
9162c0dc2a dos2unix 2011-08-03 17:50:23 +00:00
Stanislav Shwartsman
075db389a9 added atom n270 cpuid + small fixes 2011-08-03 17:49:49 +00:00
Stanislav Shwartsman
b9a44a9dbf added const to all cpudb methods 2011-08-01 18:10:48 +00:00
Stanislav Shwartsman
ea7d5e74ee fixed cpuid_limit_winnt mode 2011-07-31 21:02:04 +00:00
Stanislav Shwartsman
e958df1333 report 3dnow for amd cpudb machine 2011-07-31 20:19:09 +00:00
Stanislav Shwartsman
bccf330665 typo fix 2011-07-31 20:11:04 +00:00
Stanislav Shwartsman
d84dbcd02b fixed *x86 ISA extensions that enable this instruction* in ia_opcodes.h 2011-07-31 20:09:04 +00:00
Stanislav Shwartsman
04635ca88b small fixes 2011-07-31 19:00:56 +00:00
Stanislav Shwartsman
1d89709e62 Added another CPU to CPUDB: p4_willamette (one more without x86-64 support). 
Reimplemented CPUDB using pure C macros magic.
Fixed compilation errors when compiling with SMP on.
 2011-07-31 18:43:46 +00:00
Stanislav Shwartsman
6e6db04b8f Fixed compilation errors, dos2unix, added missed p3_katmai.txt 2011-07-31 14:56:45 +00:00
Stanislav Shwartsman
5e291e0860 Added Athlon64 Clawhammer CPUID to CPUDB 2011-07-30 21:28:16 +00:00
Stanislav Shwartsman
fefa4d5e5b added PIII Katmai to CPUDB 2011-07-30 14:30:35 +00:00
Stanislav Shwartsman
7a157cf88d fixed vmexit for xsetbv and getsec 2011-07-30 13:21:31 +00:00
Stanislav Shwartsman
6aaf9297f8 ability to turn off rdtscp 2011-07-30 09:35:20 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
37d8523ab4 fixed compilation with VMX=1 2011-07-29 18:41:17 +00:00
Stanislav Shwartsman
4ac67ec386 compilation when cu_level < 4 2011-07-29 15:24:32 +00:00