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417 Commits

Author SHA1 Message Date
Stanislav Shwartsman
aa25c1db6a name convention change - search and replace 2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
0cb0acc30f added evex decode tables - next step to populate them :) 2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
7297323c69 First step of AVX512 support implementation (simplest) 
decode and implement KMASK manipulation instructions
disasm: coming soon
 2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
a6b85d9443 compress xop tables for vex.l - smaller binary size 2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
2c9cf33b2f update (c) for few files 2013-09-05 18:37:10 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
f36364bc65 it doesn't matter if it was vex or xop ... 2013-09-05 17:52:47 +00:00
Stanislav Shwartsman
2f957bf142 re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases 2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
81affbe328 fixed incorrect lock prefix detection 2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81 decode simplification for AMD XOP prefix 2013-08-28 19:56:19 +00:00
Stanislav Shwartsman
5fe5bf1ed6 fixed alias typo corrupting avx opcodes 2013-08-27 19:45:31 +00:00
Stanislav Shwartsman
c5f72033ad correct vzeroupper opcode 2013-08-27 06:57:48 +00:00
Stanislav Shwartsman
735154a755 oops, typo bug in prev commit 2013-08-24 19:46:04 +00:00
Stanislav Shwartsman
65e6760915 small decode optimization 2013-08-24 19:29:43 +00:00
Stanislav Shwartsman
748a0da712 one more step in the way towards avx-512 which have more vector registers 2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
3a7e336cb6 more opcode alias - now VEX.W alias 2013-08-21 18:45:36 +00:00
Stanislav Shwartsman
115ec37a4c make decoder tables smaller using decode aliases 2013-08-21 04:52:49 +00:00
Stanislav Shwartsman
7005afd3a8 clean up BxRepeatable attribute - not needed anymore after VL AVX field moved to new location 2013-07-26 15:42:49 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
685e0091b4 fixed decoding of RDRAND/RDSEED with 0x66 prefix 2012-12-27 19:31:21 +00:00
Stanislav Shwartsman
9b65cae026 make WRMSR end-of-trace instruction 2012-10-25 16:49:22 +00:00
Stanislav Shwartsman
2638c1136a Add RDRAND/RDSEED instructions support (+ disasm) 
Of course no true random numbers will be generated - use standard "C" rand() function as stub.
In future it will be possible to improve (using another random generator) or even use real rdrand/rdseed intrinsics
 2012-10-09 15:16:48 +00:00
Stanislav Shwartsman
74f5bb1934 WBINVD not necessary havw to flush ICACHE 2012-09-21 08:55:10 +00:00
Stanislav Shwartsman
8044a2bda6 rename i->execute field in the instruction 
move victim cache lookup into cache lookup so traces could be linked with victim cache hits directly
 2012-09-04 15:45:05 +00:00
Stanislav Shwartsman
295e3ab8db fixed compilation warning 2012-09-02 18:38:04 +00:00
Stanislav Shwartsman
c41cbe6d56 Link traces over taken branch optimization which makes handlers chaining even more efficient. 
I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
 2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
be76f38b46 correct MOVBE decoding with prefix 0x66, also correct ADX decoding 2012-08-08 20:11:27 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
59eb1318d5 small fix 2012-05-19 19:38:57 +00:00
Stanislav Shwartsman
b5c5082ff2 Completely remove b1() field from bxInstruction structure and resuse it for AVX instructions flags. 
the iaOpcode field has no masking anymore.

fixed bug during the code reorganization:
                        
+ XOP: Fixed instructions with operands order depending on VEX.W (fixed VEX.W read from instruction object)
 2012-05-11 06:35:16 +00:00
Stanislav Shwartsman
f01e5f3e11 removed b1() from shift methods in CPU - lead to removal of b1() field from bxInstruction_c 2012-05-08 16:42:15 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
d4541f1a88 removed dedicated handler for MOVNTI - can be replaced with existing handlers 2012-02-27 15:50:43 +00:00
Stanislav Shwartsman
9bebe91826 eliminate duplicated cpu methods by adding extra param to opcodes with no modrm 2012-02-03 10:24:59 +00:00
Stanislav Shwartsman
e7ed8aca5c move inhibit interrrupts functionality to icount interface 2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
f09bdf353a RDMSR can also read TSC so make it end-of-trace as well (same as RDTSC) 2011-11-24 16:03:51 +00:00
Stanislav Shwartsman
5d9bbae71c bugfix: cant use ib2 it is overlap with disp32 2011-10-19 21:28:36 +00:00
Stanislav Shwartsman
5cc04b9955 Implemented AMDs Buldozer XOP and TBM extensions. 
XOP: few instructions are still missing, coming soon

  BX_PANIC(("VPERMILPS_VpsHpsWpsVIbR: not implemented yet"));
  BX_PANIC(("VPERMILPD_VpdHpdWpdVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VPMADCSWD_VdqHdqWdqVIbR: not implemented yet"));
  BX_PANIC(("VFRCZPS_VpsWpsR: not implemented yet"));
  BX_PANIC(("VFRCZPD_VpdWpdR: not implemented yet"));
  BX_PANIC(("VFRCZSS_VssWssR: not implemented yet"));
  BX_PANIC(("VFRCZSD_VsdWsdR: not implemented yet"));
 2011-10-19 20:54:04 +00:00
Stanislav Shwartsman
e282b5e88d Move DAZ handling into softfloat library (for float16, float32 and float64 only) and cleanup SSE and AVX code 
Fix decoding of opcodes with VEX.W=1 in 32-bit mode (AVX2, FMA)
 2011-10-01 15:40:36 +00:00
Stanislav Shwartsman
62d0c8abf7 - Now you could disable x86-64 from .bochsrc so now it is possible to emulate 
32-bit CPU using Bochs binary compiled with x86-64 support.

The commit also fixes some init.cc issues with initialization of SYSCALL/SYSRET MSR in AMD hosts and also includes code reorg.
 2011-09-25 17:36:20 +00:00
Stanislav Shwartsman
c6d07ae1b5 store modrm() for x87 in Ib() byte because x87 have no Ib() 2011-09-20 06:02:27 +00:00
Stanislav Shwartsman
50207eeb90 - Added support for AMD SSE4A emulation, the instructions can be enabled 
using .bochsrc CPUID option.
 2011-09-18 16:18:22 +00:00
Stanislav Shwartsman
e2f0880f1c support more than 32-bit cpu features vector 2011-09-14 20:22:24 +00:00
Stanislav Shwartsman
939aee87c9 handle special case - BSF/BSR vs TZCNT/LZCNT 2011-09-06 19:18:21 +00:00
Stanislav Shwartsman
e000b61cfd make RDTSC 'end of trace' instruction - guarantee that any pair ot RDTSC/RDTSCP on same CPU do not belong to same trace (and therefore will always update time and etc) - required for Win7 Thin 2011-09-06 14:13:39 +00:00
Stanislav Shwartsman
c0f5919787 small optimization 2011-09-03 15:36:40 +00:00
Stanislav Shwartsman
8099fd9efd implemented alternative access to CR8: AMD feature. Lock CR0 -> CR8 2011-09-03 15:22:56 +00:00
Stanislav Shwartsman
1f5e036695 lzcnt/tzcnt bmi instructions implemented 2011-08-31 20:43:47 +00:00
Stanislav Shwartsman
fb9da23f9b syscall/sysret are not supported outside long64 mode in Intel CPUs 2011-08-30 21:32:40 +00:00
Stanislav Shwartsman
0f73ff39df bug fix 2011-08-30 19:16:08 +00:00
Stanislav Shwartsman
c30275016e avx2 added broadcast from register 2011-08-29 21:00:25 +00:00
Stanislav Shwartsman
6bdfbeeffa fixed for gather VSIB calculation 2011-08-28 20:14:53 +00:00
Stanislav Shwartsman
239c5a449d added 'locked' information to bxInstruction_c for instrumentation and other future use 2011-08-27 20:09:18 +00:00
Stanislav Shwartsman
44241a1e56 - Added support for AVX and AVX2 instructions emulation, to enable configure 
with --enable-avx option. When compiled in, AVX still has to be enabled
    using .bochsrc CPUID option. AVX2 FMA instructions still not implemented.

  - Added support for Bit Manipulation Instructions (BMI) emulation. The BMI
    instructions support can be enabled using .bochsrc CPUID option.
 2011-08-27 13:47:16 +00:00
Stanislav Shwartsman
e48765a511 VMX fixed, cleanups 2011-07-29 20:22:35 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
08ba847ce4 fix bug inserted with prev commit + cleanup 2011-06-28 16:04:40 +00:00
Stanislav Shwartsman
68f96846fe no need to define 3b opcodes on < 80x686 2011-06-26 19:39:48 +00:00
Stanislav Shwartsman
2f582db722 compile less stuff for cpu-level=5 2011-06-26 19:15:30 +00:00
Stanislav Shwartsman
beafa7c88b improved x86 hw code bp handling 2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
29e3f6e762 remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache 2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
a02ddb36d2 undo a change from 2 weeks ago that cause correctness failure 2011-05-06 08:03:45 +00:00
Stanislav Shwartsman
c44f82f4ac small cleanup 2011-04-25 20:26:22 +00:00
Stanislav Shwartsman
024a1ace38 move X2APIC to be .bochsrc option, rework of the cpuid code 2011-04-21 13:27:42 +00:00
Stanislav Shwartsman
69b829a935 small fixes 2011-04-12 06:05:31 +00:00
Stanislav Shwartsman
0de9a5f75d compilation fix 2011-04-08 16:20:26 +00:00
Stanislav Shwartsman
4de76b0571 introduced victim cache for a trace cache structure. 
Allows to significantly  cut trace cache miss latenct and find data in victim cahe instead of redoding it 
8 entries VC in parallel with direct map 64K entries
 2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
7664c55b08 first fixups after AVX 
(and for AVX)
 2011-03-20 18:27:31 +00:00
Stanislav Shwartsman
7ced718040 implemented AVX instructions support 
many changes - some cleanup will follow
please report ay found bugs !
 2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
2d3f3668c7 Fixed IRET 64-bit mode bug 
Support for 32 float copare methods for AVX
ckeanups in fetchdecode
 2011-02-13 06:10:11 +00:00
Stanislav Shwartsman
a31103e7d8 optimize fetchdecode tables - part2 2011-01-21 16:07:51 +00:00
Stanislav Shwartsman
fbc9b8b190 phase1 of opcode tables optimization 2011-01-20 16:24:42 +00:00
Stanislav Shwartsman
8c5c078b13 optimize sse and mmx code 2011-01-16 20:42:28 +00:00
Stanislav Shwartsman
a80b44b6db split more sse ops 2011-01-09 20:18:02 +00:00
Stanislav Shwartsman
a1bc92a46b split more SSE opcodes 2011-01-08 11:20:29 +00:00
Stanislav Shwartsman
205351f44e Split R/M all SSE fetchdecode tables 
- next step optimize tables
 2011-01-08 09:53:52 +00:00
Stanislav Shwartsman
f9f868247a split more SSE ops 2010-12-30 20:35:10 +00:00
Stanislav Shwartsman
25b1e2e58d split more SSE ops 2010-12-26 20:41:47 +00:00
Stanislav Shwartsman
c005444d5b split more SSE opcodes 2010-12-25 07:59:15 +00:00
Stanislav Shwartsman
fee7a91d86 Fixed compilation with cpu-level=3 2010-12-24 16:34:55 +00:00
Stanislav Shwartsman
040a8e1a3a split bunch of SSE opcodes 2010-12-24 08:35:00 +00:00
Stanislav Shwartsman
43600f3756 complete rework of SSE code 
next step - split all SSE opcodes by ModC0
 2010-12-22 21:16:02 +00:00
Stanislav Shwartsman
29a674e520 split rd/wr CR opcodes for simplicity 2010-12-19 22:36:19 +00:00
Stanislav Shwartsman
d60b7c0919 rename accessor for opcodeReg() in instruction 2010-12-06 21:45:56 +00:00
Stanislav Shwartsman
49c85b07f6 Fixed address size wrap 2010-10-18 22:19:45 +00:00
Stanislav Shwartsman
f655e33779 imm mode2 could be only with imm_mode1 2010-09-25 10:17:04 +00:00
Stanislav Shwartsman
75f2ae9c18 fetchdecode simplification rework 2010-09-25 09:55:40 +00:00
Stanislav Shwartsman
369aba757d style change 2010-09-23 20:38:02 +00:00
Stanislav Shwartsman
a0705392d3 Fixed failure on BE hosts 2010-09-12 17:33:34 +00:00
Stanislav Shwartsman
1107ce138e small fetchdecode optimization 2010-09-07 19:54:50 +00:00
Stanislav Shwartsman
55cb12badf fixed missed canonical failure on system access 2010-07-22 20:12:25 +00:00
Stanislav Shwartsman
67aec1dc22 warning fix 2010-05-26 18:37:54 +00:00
Stanislav Shwartsman
84880793f3 optimize for speed 2010-05-26 18:34:25 +00:00
Stanislav Shwartsman
8d8d1590f5 fetchdecide rework for AVX (0xF3 SSE prefix encoded as 2 in VEX) 2010-05-23 19:17:41 +00:00
Stanislav Shwartsman
1c00193616 cleanup 2010-05-22 10:43:39 +00:00
Stanislav Shwartsman
fff0a79aea a little simpler fetchdecode 2010-05-21 21:17:32 +00:00
Stanislav Shwartsman
3dfcfd0ccd Split shift opcodes | optimize SAR opcode 2010-05-18 07:28:05 +00:00
Stanislav Shwartsman
9c69b15ecb fetchdecode tables reorg phase1 2010-05-13 05:38:24 +00:00