- move per VP data into struct sadata_vp referenced from l->l_savp
* VP id
* lock on VP data
* LWP on VP
* recently blocked LWP on VP
* queue of LWPs woken which ran on this VP before sleep
* faultaddr
* LWP cache for upcalls
* upcall queue
- add current concurrency and requested concurrency variables
- make process exit run LWP on all VPs
- make signal delivery consider all VPs
- make timer events consider all VPs
- add sa_newsavp to allocate new sadata_vp structure
- add sa_increaseconcurrency to prepare new VP
- make sys_sa_setconcurrency request new VP or wakeup idle VP
- make sa_yield lower current concurrency
- set sa_cpu = VP id in upcalls
- maintain cached LWPs per VP
drivers that attach to it. This allows for other host interface chips
that use the same keyboards and mice, such as the ones in the ARM
IOMD20, ARM7500, and SA-1111. The PC-compatible driver is still
called pckbc(4), and the new abstraction layer is "pckbport", so the
child devices have moved from sys/dev/pckbc to sys/dev/pckbport, which
also contains some code shared between all host controllers. To avoid
incompatibility, pckbdreg.h is still installed in
/usr/include/dev/pckbc.
In theory, this shouldn't cause any behavioural changes in the drivers
concerned. Thy just use rather more function pointers than before. Tested
on i386 and (with a new host driver) acorn32. Compiled on several other
affected architectures.
lcd driver can be configured with or without wsdisplay.
With wsdisplay, it supports text mode using rasops in 8bpp or 16bpp.
Without it, users only can mmap(2) the framebuffer.
XXX: 1-, 2-, 4-, or 24- bpp mode is not supported yet.
XXX: S3C24x0's LCD controller can have virtual screen which is bigger
than actual LCD panel. Our wsdisplay framework doesn't have
features to utilize it.
interrupts; some boards actually use those GPIO pins as external
interrupt sources.
Instead, assign soft interrupt bits to on-chip sources which are
not used by the IXP425 port.
up attached at the same time, and so that they can both prevent the forthcoming
iomdkbc(4) attaching to the keyboard slot.
[ file missed in last commit ]
obmitted resulting in a compilation failure in the autobuilds.
It effectively removes the now redundant reference to "beep.h" and removes
an associated prototype that wasn't used.
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).
When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).
Just before removing the vector page mapping, switch to the kernel
pmap's L1/vector page mapping so as not to pull the rug out from
under ourselves.
To prevent the stale L1/vector page mapping from being restored by
cpu_switch, replace the relevant fields of the dying process' pcb
with those of lwp0's pcb.
Remove the vestigal sysbeep device and replace it with the same kind of
mechanism that pckbd(4) uses to find the bell, which is just as ugly, but
more standard. Adapt beep(4) to the new world (though I'm not sure it
deserves to live).
8-bit VIDC audio. Both Richard Earnshaw and I had guessed that a set
bit was positive (the same as normal mu-law), but the AudioWorks
manual, and Sound_SoundLog on RISC OS, seem to disagree. Change
MULAW_TO_VIDC to match Sound_SoundLog, since the latter is probably
definitive.
process context ('reaper').
From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
as FPU state), and is the last potentially blocking operation;
all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
for both 'process' and 'lwp' exit
uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.
MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.
g/c now unneeded routines and variables, including the reaper kernel thread
acccesses with addresses shifted by the amount specified in the cookie.
Also make the inclusion of the wscons file the resposibility of whoever
includes files.iomd. (found while attempting to checking riscstation
support into evbarm)
is naughty even if it does work), find out the complete list of physical pages
we'll have to DMA from in vidcaudio_trigger_output() and save it for use by
the interrupt handler.
had ever worked, but if it had, it had bit-rotted so far that it
almost all needed replacing. The new version support both 8-bit sound
on the VIDC20 and 16-bit sound on the ARM7500 and ARM7500FE.
sysbeep() support has been lost, but I'm not sure whether that belongs
here or in audio(4) anyway. Support for 16-bit sound on the VIDC20
isn't present because I don't have the hardware to test it. Donations
welcome!
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.
This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.
On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.
exactly twice by me) which causes the code at the top of copyin which
word-aligns the destination pointer to copy more bytes than necessary,
resulting in an alignment fault later on.
The bug is difficult to reproduce, but as far as I can tell it seems
to be as a result of the condition codes being corrupted, possibly
following a page fault caused by the first ldrbt/strb instructions.
The subsequent ldr<cc>bt/str<cc>b instructions then _always_ execute.
I can't think of any obvious reason why this would happen, though.
base offset before using it. This makes it work the same as every other
implementation, and makes wdc at pioc on acorn32 work again. Fix the only
caller I found which depended on the old behaviour.
Gone are the old kern_sysctl(), cpu_sysctl(), hw_sysctl(),
vfs_sysctl(), etc, routines, along with sysctl_int() et al. Now all
nodes are registered with the tree, and nodes can be added (or
removed) easily, and I/O to and from the tree is handled generically.
Since the nodes are registered with the tree, the mapping from name to
number (and back again) can now be discovered, instead of having to be
hard coded. Adding new nodes to the tree is likewise much simpler --
the new infrastructure handles almost all the work for simple types,
and just about anything else can be done with a small helper function.
All existing nodes are where they were before (numerically speaking),
so all existing consumers of sysctl information should notice no
difference.
PS - I'm sorry, but there's a distinct lack of documentation at the
moment. I'm working on sysctl(3/8/9) right now, and I promise to
watch out for buses.
In the interrupt dispatch loop, make sure to handle any pending interrupts
which came in while we were dealing with the first interrupt(s), and which
are enabled at the current spl.
This fixes a problem where the intr_enabled/hw mask is not updated to
allow pending interrupts through until the next splx(). In some case,
interrupts could be delayed until the next clock tick.
which came in while we were dealing with the first interrupt(s), and which
are enabled at the current spl.
This fixes a problem where the intr_enabled/hw mask is not updated to
allow pending interrupts through until the next splx(). In some case,
interrupts could be delayed until the next clock tick.
the functionality of ixp425_bs_tag.
- Add missing stream_{read,write}_1 ops to ixp425_bs_tag.
- Re-work the delay() implementation to use the free-running Time-
Stamp counter. This removes the need to bootstrap TMR0 early on.
the idle loop. They seem to have gone AWOL sometime in the past.
Fixes port-arm/23390.
- While here, tidy up the idle loop.
- Add a cheap DIAGNOSTIC check for run queue sanity.
returns non-zero and we want to shortcut out. This avoids a bogus pagefault
condition being detected in sa_switch().
Many thanks to Christian Limpach for finding this, obviating my band-aid
patch to kern_sa.c (posted on tech-kern).
the call to data_abort_fixup() as the fixup routines also try to
de-reference the fault pc.
- If a fault came from kernel mode, and the fault address looks to be in
the kernel's address space, and pcb_onfault is *set*, check the
instruction which caused the fault. If it's LDR{B,}T or STR{B,}T
then one of the copy in/out routines is trying to read/write a
kernel address with the wrong privilege. If that address is actually
mapped, we could end up in an infinite loop because we failed to
notice that it's really a 'user mode' access. Yay for "crashme".
I suspect this also fixes PR port-arm/23052.
Note: This *could* be fixed by adding sanity checks to copyin et al,
but that would add extra overhead to the non-error path...
- Fix a couple of __predict_false cases.
to determine if a fault is read or write, make sure tf->tf_pc is 32-bit
aligned before dereferencing it.
Otherwise, deliver an illegal instruction signal to the process. We don't
support execution of Thumb code at this time.
copyin() or copyout().
uvm_useracc() tells us whether the mapping permissions allow access to
the desired part of an address space, and many callers assume that
this is the same as knowing whether an attempt to access that part of
the address space will succeed. however, access to user space can
fail for reasons other than insufficient permission, most notably that
paging in any non-resident data can fail due to i/o errors. most of
the callers of uvm_useracc() make the above incorrect assumption. the
rest are all misguided optimizations, which optimize for the case
where an operation will fail. we'd rather optimize for operations
succeeding, in which case we should just attempt the access and handle
failures due to insufficient permissions the same way we handle i/o
errors. since there appear to be no good uses of uvm_useracc(), we'll
just remove it.
alignment fault checking if necessary.
This option gets the acorn32 port working again.
XXX: Richard Earnshaw suggested enabling alignment faults for
XXX: userland only on acorn32. Need to investigate this.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)
containing signal posting, kernel-exit handling and sa_upcall processing.
XXX the pc532, sparc, sparc64 and vax ports should have their
XXX userret() code rearranged to use this.
- Assume a permission fault is always the result of an attempted
write, so no need to disassemble the opcode.
(as discussed with Richard Earnshaw/Jason Thorpe a week or two ago)
- Split out non-MMU data aborts into separate functions, and deal
correctly with XScale imprecise aborts. Specifically, the old code
made no attempt to handle the double abort faults which can occur
as a result of two consecutive external (imprecise) aborts. This
was easy to provoke by read(2)ing from a /dev/mem offset which caused
an external abort. With the old code, this would bring the system
down instantly, with little clue as to why. (hint: tf_spsr held
PSR_ABT32_MODE...)
- Re-write badaddr_read() to use pcb_onfault instead of adding extra
overhead to data_abort_handler(). A side effect of this is that it
now benefits from the XScale double abort recovery.
- Invoke the cpu-specific prefetch/data abort fixup routines only if
the host cpu actually needs it. On other cpus, the code is optimised
away.
- Sprinkle __predict_{false,true} in all the right places.
- G/C some excess debugging baggage.
needless duplication.
Additionally, merge AST handling into the same code.
exception.S and the generic irq_dispatch.S routines have been updated
to use the macroes.
XXX: I have patches for the non-generic IRQ dispatch routines, but they
need testing by someone with hardware.
flushed on every context switch as an indicator that a mapping is
not resident in the cache.
Instead, used the per-pmap flag maintained by the cpu_switch/pmap code.
Enable alignment faults on arm32 for both kernel and userland.
If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.
If COMPAT_15 and EXEC_AOUT are defined, support per-process
alignment checking where AFLTs are always enabled when running
kernel code and userland ELF binaries, and dynamically disabled/
enabled when switching to/from a.out binaries. This is necessary
in order to execute older a.out binaries, where gcc made
deliberate use of misaligned loads under certain circumstances.
precision back to machine-dependent headers. C99 has no strict
requirement which, if any, extended-precision type `long double' must
match, and even between 80-bit formats there are differences in
implementation (m68k vs. x86).
* On arm, consider __VFP_FP__.
instead.
With this change, we no longer need to save the current interrupt level
in the switchframe. This is no great loss since both cpu_switch and
cpu_switchto are always called at splsched, so the process' spl is
effectively saved somewhere in the callstack.
This fixes an evbarm problem reported by Allen Briggs:
lwp gets into sa_switch -> mi_switch with newl != NULL
when it's the last element on the runqueue, so it
hits the second bit of:
if (newl == NULL) {
retval = cpu_switch(l, NULL);
} else {
remrunqueue(newl);
cpu_switchto(l, newl);
retval = 0;
}
mi_switch calls remrunqueue() and cpu_switchto()
cpu_switchto unlocks the sched lock
cpu_switchto drops CPU priority
softclock is received
schedcpu is called from softclock
schedcpu hits the first if () {} block here:
if (l->l_priority >= PUSER) {
if (l->l_stat == LSRUN &&
(l->l_flag & L_INMEM) &&
(l->l_priority / PPQ) != (l->l_usrpri / PPQ)) {
remrunqueue(l);
l->l_priority = l->l_usrpri;
setrunqueue(l);
} else
l->l_priority = l->l_usrpri;
}
Since mi_switch has already run remrunqueue, the LWP has been
removed, but it's not been put back on any queue, so the
remrunqueue panics.
- Use the "clz" instruction to pick a run-queue, instead of using the
ffs-by-table-lookup method.
- Use strd instead of stmia where possible.
- Use multiple ldr instructions instead of ldmia where possible.
they use the mini D$.
This results in a small performance boost on xscale platforms, since
flushing the main cache on a context switch won't affect the kernel
stack/pcb.
* _UC_MACHINE_PC() - access the program counter
* _UC_MACHINE_INTRV() - access the integer return value register
* _UC_MACHINE_SET_PC() - set the program counter (this requires
special handling on some platforms).
GPIO interrupt, check the GPIO interrupt status register after clearing
it down to see if the interrupt source has disappeared. If it does,
assume it was a spurious event. Otherwise, panic.
- Move board-specific PCI/GPIO initialisation to its rightful place.
- Handle clearing down latched GPIO interrupts in a board-independent way.
- Use MI com(4) driver for on-chip UARTs.
- Misc. tidying up.
Tested on IXDP425.
<sys/bootblock.h>:
* Added definitions for the Master Boot Record (MBR) used by
a variety of systems (primarily i386), including the format
of the BIOS Parameter Block (BPB).
This information was cribbed from a variety of sources
including <sys/disklabel_mbr.h> which this is a superset of.
As part of this, some data structure elements and #defines
were renamed to be more "namespace friendly" and consistent
with other bootblocks and MBR documentation.
Update all uses of the old names to the new names.
<sys/disklabel_mbr.h>:
* Deprecated in favor of <sys/bootblock.h> (the latter is more
"host tool" friendly).
amd64 & i386:
* Renamed /usr/mdec/bootxx_dosfs to /usr/mdec/bootxx_msdos, to
be consistent with the naming convention of the msdosfs tools.
* Removed /usr/mdec/bootxx_ufs, as it's equivalent to bootxx_ffsv1
and it's confusing to have two functionally equivalent bootblocks,
especially given that "ufs" has multiple meanings (it could be
a synonym for "ffs", or the group of ffs/lfs/ext2fs file systems).
* Rework pbr.S (the first sector of bootxx_*):
+ Ensure that BPB (bytes 11..89) and the partition table
(bytes 446..509) do not contain code.
+ Add support for booting from FAT partitions if BOOT_FROM_FAT
is defined. (Only set for bootxx_msdos).
+ Remove "dummy" partition 3; if people want to installboot(8)
these to the start of the disk they can use fdisk(8) to
create a real MBR partition table...
+ Compile with TERSE_ERROR so it fits because of the above.
Whilst this is less user friendly, I feel it's important
to have a valid partition table and BPB in the MBR/PBR.
* Renamed /usr/mdec/biosboot to /usr/mdec/boot, to be consistent
with other platforms.
* Enable SUPPORT_DOSFS in /usr/mdec/boot (stage2), so that
we can boot off FAT partitions.
* Crank version of /usr/mdec/boot to 3.1, and fix some of the other
entries in the version file.
installboot(8) (i386):
* Read the existing MBR of the filesystem and retain the BIOS
Parameter Block (BPB) in bytes 11..89 and the MBR partition
table in bytes 446..509. (Previously installboot(8) would
trash those two sections of the MBR.)
mbrlabel(8):
* Use sys/lib/libkern/xlat_mbr_fstype.c instead of homegrown code
to map the MBR partition type to the NetBSD disklabel type.
Test built "make release" for i386, and new bootblocks verified to work
(even off FAT!).
Right now the only flag is used to indicate if a ksiginfo_t is a
result of a trap. Add a predicate macro to test for this flag.
* Add initialization macros for ksiginfo_t's.
* Add accssor macro for ksi_trap. Expands to 0 if the ksiginfo_t was
not the result of a trap. This matches the sigcontext trapcode semantics.
* In kpsendsig(), use KSI_TRAP_P() to select the lwp that gets the signal.
Inspired by Matthias Drochner's fix to kpsendsig(), but correctly handles
the case of non-trap-generated signals that have a > 0 si_code.
This patch fixes a signal delivery problem with threaded programs noted by
Matthias Drochner on tech-kern.
As discussed on tech-kern. Reviewed and OK's by Christos.
interface controllers (of varying intelligence levels).
Contributed by Wasabi Systems, Inc. Primarily written by Steve Woodford,
with some modification by me.
(NOTE: "cvs ci" was missed on this directory during the initial checkin
of the new I2C code.)
which is automatically included during kernel config, and add comments
to individual machine-dependant majors.* files to assign new MI majors
in MI file.
Range 0-191 is reserved for machine-specific assignments, range
192+ are MI assignments.
Follows recent discussion on tech-kern@
interface controllers (of varying intelligence levels).
Contributed by Wasabi Systems, Inc. Primarily written by Steve Woodford,
with some modification by me.
but there are very small diffs in register definitions. For that, add
new options SSCOM_S3C{2800,2410,2400} and include appropriate
s3c*reg.h.
SSCOM_S3C2410 is also needed for interrupt controller differences.
