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On Xscale, define PMAP_UAREA() and use it to tweak uarea mappings so 

they use the mini D$.

This results in a small performance boost on xscale platforms, since
flushing the main cache on a context switch won't affect the kernel
stack/pcb.
This commit is contained in:
scw 2003-10-13 20:50:34 +00:00
parent 4355b16f71
commit 063066a055
2 changed files with 64 additions and 4 deletions
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60
sys/arch/arm/arm32/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.140 2003/10/05 19:44:58 matt Exp $ */
/* $NetBSD: pmap.c,v 1.141 2003/10/13 20:50:34 scw Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@ -212,7 +212,7 @@
#include <machine/param.h>
#include <arm/arm32/katelib.h>
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.140 2003/10/05 19:44:58 matt Exp $");
__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.141 2003/10/13 20:50:34 scw Exp $");
#ifdef PMAP_DEBUG
@ -4731,6 +4731,10 @@ pmap_pte_init_sa1(void)
#endif /* ARM_MMU_SA1 == 1*/
#if ARM_MMU_XSCALE == 1
#if (ARM_NMMUS > 1)
static u_int xscale_use_minidata;
#endif
void
pmap_pte_init_xscale(void)
{
@ -4805,6 +4809,10 @@ pmap_pte_init_xscale(void)
pte_l2_s_cache_mode = L2_C;
}
#if (ARM_NMMUS > 1)
xscale_use_minidata = 1;
#endif
pte_l2_s_prot_u = L2_S_PROT_U_xscale;
pte_l2_s_prot_w = L2_S_PROT_W_xscale;
pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
@ -4895,6 +4903,49 @@ xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa)
:
: "r" (auxctl));
}
/*
* Change the PTEs for the specified kernel mappings such that they
* will use the mini data cache instead of the main data cache.
*/
void
pmap_uarea(vaddr_t va)
{
struct l2_bucket *l2b;
pt_entry_t *ptep, *sptep, pte;
vaddr_t next_bucket, eva;
#if (ARM_NMMUS > 1)
if (xscale_use_minidata == 0)
return;
#endif
eva = va + USPACE;
while (va < eva) {
next_bucket = L2_NEXT_BUCKET(va);
if (next_bucket > eva)
next_bucket = eva;
l2b = pmap_get_l2_bucket(pmap_kernel(), va);
KDASSERT(l2b != NULL);
sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
while (va < next_bucket) {
pte = *ptep;
if (!l2pte_minidata(pte)) {
cpu_dcache_wbinv_range(va, PAGE_SIZE);
cpu_tlb_flushD_SE(va);
*ptep = pte & ~L2_B;
}
ptep++;
va += PAGE_SIZE;
}
PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
}
cpu_cpwait();
}
#endif /* ARM_MMU_XSCALE == 1 */
#if defined(DDB)
@ -4982,7 +5033,10 @@ pmap_dump(pmap_t pm)
ch = 'B'; /* No cache buff */
break;
case 0x08:
ch = 'C'; /* Cache No buff */
if (pte & 0x40)
ch = 'm';
else
ch = 'C'; /* Cache No buff */
break;
case 0x0c:
ch = 'F'; /* Cache Buff */

8
sys/arch/arm/include/arm32/pmap.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */
/* $NetBSD: pmap.h,v 1.77 2003/10/13 20:50:34 scw Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@ -377,6 +377,9 @@ do { \
#define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
#define l2pte_valid(pte) ((pte) != 0)
#define l2pte_pa(pte) ((pte) & L2_S_FRAME)
#define l2pte_minidata(pte) (((pte) & \
(L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
== (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
/* L1 and L2 page table macros */
#define pmap_pde_v(pde) l1pte_valid(*(pde))
@ -420,6 +423,9 @@ void pmap_zero_page_xscale(paddr_t);
void pmap_pte_init_xscale(void);
void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
#define PMAP_UAREA(va) pmap_uarea(va)
void pmap_uarea(vaddr_t);
#endif /* ARM_MMU_XSCALE == 1 */
extern pt_entry_t pte_l1_s_cache_mode;