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As per the recent ixp425 fix (which is based on this code): 

In the interrupt dispatch loop, make sure to handle any pending interrupts
which came in while we were dealing with the first interrupt(s), and which
are enabled at the current spl.

This fixes a problem where the intr_enabled/hw mask is not updated to
allow pending interrupts through until the next splx(). In some case,
interrupts could be delayed until the next clock tick.
This commit is contained in:
scw 2003-12-03 19:55:37 +00:00
parent bcb37dc972
commit ef87776bdb
1 changed files with 8 additions and 2 deletions
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10
sys/arch/arm/xscale/i80321_icu.c
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@ -1,4 +1,4 @@
/* $NetBSD: i80321_icu.c,v 1.8 2003/07/15 00:24:53 lukem Exp $ */
/* $NetBSD: i80321_icu.c,v 1.9 2003/12/03 19:55:37 scw Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.8 2003/07/15 00:24:53 lukem Exp $");
__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.9 2003/12/03 19:55:37 scw Exp $");
#ifndef EVBARM_SPL_NOINLINE
#define EVBARM_SPL_NOINLINE
@ -513,6 +513,12 @@ i80321_intr_dispatch(struct clockframe *frame)
/* Re-enable this interrupt now that's it's cleared. */
intr_enabled |= ibit;
i80321_set_intrmask();
/*
* Don't forget to include interrupts which may have
* arrived in the meantime.
*/
hwpend |= ((i80321_ipending & ICU_INT_HWMASK) & ~pcpl);
}
/* Check for pendings soft intrs. */