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The PIRSR is at location 0xffffe1ec, not 0xffffe2ec. 

Source: Intel(R) 80321 I/O Processor Developer's Manual, page 578
This commit is contained in:
gavan 2003-12-16 00:04:09 +00:00
parent d9948df6dd
commit 5232db351e
1 changed files with 3 additions and 3 deletions
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6
sys/arch/arm/xscale/i80321reg.h
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@ -1,4 +1,4 @@
/* $NetBSD: i80321reg.h,v 1.12 2003/10/06 16:06:05 thorpej Exp $ */
/* $NetBSD: i80321reg.h,v 1.13 2003/12/16 00:04:09 gavan Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@ -316,10 +316,10 @@
* INTSTR cp6 c4,0 0xffffe7d4
* IINTSRC cp6 c8,0 0xffffe7d8
* FINTSRC cp6 c9,0 0xffffe7dc
* PIRSR 0xffffe2ec
* PIRSR 0xffffe1ec
*/
#define ICU_PIRSR 0x02ec
#define ICU_PIRSR 0x01ec
#define ICU_GPOE 0x07c4
#define ICU_GPID 0x07c8
#define ICU_GPOD 0x07cc